December 2013 - flashrom - mail.coreboot.org

[PATCH] CID1130005: Array compared against 0

by Stefan Reinauer

CID1130005: Array compared against 0 The address of an array is never NULL, so the comparison will always evaluate the same way. In selfcheck: Array compared against NULL pointer Since the array is defined unconditionally in C code the check does not really make sense. It might make more sense to check whether there are entries in the array, but that is not required on all platforms so far. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Index: print.c =================================================================== --- print.c (revision 1763) +++ print.c (working copy) @@ -1073,7 +1073,7 @@ B("ZOTAC", "ZBOX HD-ID11", OK, NULL, NULL), #endif - {0}, + {NULL}, }; /* Please keep this list alphabetically ordered by vendor/board. */ @@ -1101,6 +1101,6 @@ B("Lenovo", "3000 V100 TF05Cxx", OK, "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo3…", NULL), #endif - {0}, + {NULL}, }; #endif Index: flashrom.c =================================================================== --- flashrom.c (revision 1763) +++ flashrom.c (working copy) @@ -1759,24 +1759,6 @@ if (selfcheck_eraseblocks(chip)) ret = 1; -#if CONFIG_INTERNAL == 1 - if (chipset_enables == NULL) { - msg_gerr("Chipset enables table does not exist!\n"); - ret = 1; - } - if (board_matches == NULL) { - msg_gerr("Board enables table does not exist!\n"); - ret = 1; - } - if (boards_known == NULL) { - msg_gerr("Known boards table does not exist!\n"); - ret = 1; - } - if (laptops_known == NULL) { - msg_gerr("Known laptops table does not exist!\n"); - ret = 1; - } -#endif return ret; }

6 years, 1 month

3
13
0 0

[PATCH] Unlock ST M50FW002 correctly

by Carl-Daniel Hailfinger

Unlock ST M50FW002 correctly Refactor ST M50 family unlocking TODO: Unify write_lockbits_49fl00x() and unlock_block_stm50() and unlock_w39_fwh_block() and unlock_82802ab() and write_lockbits_block_49lfxxxc(). They all use exactly the same mechanism, but they don't share any code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-stm50fw002_unlock/flashchips.c =================================================================== --- flashrom-stm50fw002_unlock/flashchips.c (Revision 1437) +++ flashrom-stm50fw002_unlock/flashchips.c (Arbeitskopie) @@ -7523,9 +7523,9 @@ .total_size = 256, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_82802ab, - .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (sst49lfxxxc.c) */ + .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (82802ab.c) */ .block_erasers = { { @@ -7536,9 +7536,12 @@ {16 * 1024, 1}, }, .block_erase = erase_block_82802ab, + }, { + .eraseblocks = { {256 * 1024, 1}, }, + .block_erase = NULL, /* Only in A/A mux mode */ } }, - .unlock = unlock_stm50flw0x0x, + .unlock = unlock_stm50fw002, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ Index: flashrom-stm50fw002_unlock/stm50flw0x0x.c =================================================================== --- flashrom-stm50fw002_unlock/stm50flw0x0x.c (Revision 1437) +++ flashrom-stm50fw002_unlock/stm50flw0x0x.c (Arbeitskopie) @@ -3,6 +3,7 @@ * * Copyright (C) 2008 Claus Gindhart <claus.gindhart(a)kontron.com> * Copyright (C) 2009 Sean Nelson <audiohacked(a)gmail.com> + * Copyright (C) 2011 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,6 +32,21 @@ #include "flashchips.h" #include "chipdrivers.h" +#define STM50_UNLOCKED 0x00 + +static int unlock_block_stm50(struct flashchip *flash, int offset) +{ + chipaddr lock = flash->virtual_registers + offset + 2; + + msg_cdbg("Unlocking at 0x%x\n", offset); + chip_writeb(STM50_UNLOCKED, lock); + if (chip_readb(lock) != STM50_UNLOCKED) { + msg_cerr("Cannot unlock at 0x%x\n", offset); + return -1; + } + return 0; +} + /* * claus.gindhart(a)kontron.com * The ST M50FLW080B and STM50FLW080B chips have to be unlocked, @@ -38,8 +54,6 @@ */ static int unlock_block_stm50flw0x0x(struct flashchip *flash, int offset) { - chipaddr wrprotect = flash->virtual_registers + 2; - static const uint8_t unlock_sector = 0x00; int j; /* @@ -58,22 +72,12 @@ || (offset == 0xF0000)) { // unlock each 4k-sector - for (j = 0; j < 0x10000; j += 0x1000) { - msg_cdbg("unlocking at 0x%x\n", offset + j); - chip_writeb(unlock_sector, wrprotect + offset + j); - if (chip_readb(wrprotect + offset + j) != unlock_sector) { - msg_cerr("Cannot unlock sector @ 0x%x\n", - offset + j); + for (j = 0; j < 0x10000; j += 0x1000) + if (unlock_block_stm50(flash, offset + j)) return -1; - } - } } else { - msg_cdbg("unlocking at 0x%x\n", offset); - chip_writeb(unlock_sector, wrprotect + offset); - if (chip_readb(wrprotect + offset) != unlock_sector) { - msg_cerr("Cannot unlock sector @ 0x%x\n", offset); + if (unlock_block_stm50(flash, offset)) return -1; - } } return 0; @@ -93,6 +97,27 @@ return 0; } +/* FIXME: Should this be moved to a generic walk_unlockregions()? */ +int unlock_stm50fw002(struct flashchip *flash) +{ + static const struct eraseblock unlockregions[4] = { + {64 * 1024, 3}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}}; + int i, j; + int addr = 0; + + for (i = 0; i < 4; i++) { + for (j = 0; j < unlockregions[i].count; j++) { + if (unlock_block_stm50(flash, addr)) + return 1; + addr += unlockregions[i].size; + } + } + return 0; +} + /* This function is unused. */ int erase_sector_stm50flw0x0x(struct flashchip *flash, unsigned int sector, unsigned int sectorsize) { Index: flashrom-stm50fw002_unlock/chipdrivers.h =================================================================== --- flashrom-stm50fw002_unlock/chipdrivers.h (Revision 1437) +++ flashrom-stm50fw002_unlock/chipdrivers.h (Arbeitskopie) @@ -146,5 +146,6 @@ /* stm50flw0x0x.c */ int erase_sector_stm50flw0x0x(struct flashchip *flash, unsigned int block, unsigned int blocksize); int unlock_stm50flw0x0x(struct flashchip *flash); +int unlock_stm50fw002(struct flashchip *flash); #endif /* !__CHIPDRIVERS_H__ */ -- http://www.hailfinger.org/

6 years, 1 month

3
3
0 0

[PATCH] CID1129998/1129999: Unchecked return value from library

by Stefan Reinauer

CID1129998/1129999: Unchecked return value from library The function returns a value that indicates an error condition. If this is not checked, the error condition may not be handled correctly. In serialport_write_nonblock: Value returned from a library function is not checked for errors before being used. This value may indicate an error condition. In serialport_config: Value returned from a library function is not checked for errors before being used. This value may indicate an error condition. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Index: serial.c =================================================================== --- serial.c (revision 1763) +++ serial.c (working copy) @@ -181,7 +181,10 @@ msg_pdbg("Baud rate is %ld.\n", dcb.BaudRate); #else struct termios wanted, observed; - fcntl(fd, F_SETFL, 0); + if (fcntl(fd, F_SETFL, 0) != 0) { + msg_perr_strerror("Could not set serial port mode: "); + return 1; + } if (tcgetattr(fd, &observed) != 0) { msg_perr_strerror("Could not fetch original serial port configuration: "); return 1; @@ -419,14 +422,21 @@ return -1; } if(!SetCommTimeouts(sp_fd, &newTimeout)) { + msg_perr_strerror("Could not set serial port timeout settings: "); + return -1; + } #else ssize_t rv; const int flags = fcntl(sp_fd, F_GETFL); + if (flags == -1) { + msg_perr_strerror("Could not get serial port mode: "); + return -1; + } if (fcntl(sp_fd, F_SETFL, flags | O_NONBLOCK) != 0) { -#endif - msg_perr_strerror("Could not set serial port timeout settings %s"); + msg_perr_strerror("Could not set serial port mode to non-blocking: "); return -1; } +#endif int i; int rd_bytes = 0; @@ -458,12 +468,15 @@ /* restore original blocking behavior */ #ifdef _WIN32 if (!SetCommTimeouts(sp_fd, &oldTimeout)) { + msg_perr_strerror("Could not set serial port timeout settings: "); + ret = -1; + } #else if (fcntl(sp_fd, F_SETFL, flags) != 0) { -#endif - msg_perr_strerror("Could not restore serial port timeout settings: %s\n"); + msg_perr_strerror("Could not set serial port mode to non-blocking: "); ret = -1; } +#endif return ret; } @@ -495,7 +508,14 @@ #else ssize_t rv; const int flags = fcntl(sp_fd, F_GETFL); - fcntl(sp_fd, F_SETFL, flags | O_NONBLOCK); + if (flags == -1) { + msg_perr_strerror("Could not get serial port mode: "); + return -1; + } + if (fcntl(sp_fd, F_SETFL, flags | O_NONBLOCK) != 0) { + msg_perr_strerror("Could not set serial port mode to non-blocking: "); + return -1; + } #endif int i; @@ -531,10 +551,13 @@ #ifdef _WIN32 if (!SetCommTimeouts(sp_fd, &oldTimeout)) { msg_perr_strerror("Could not restore serial port timeout settings: "); + return -1; + } #else if (fcntl(sp_fd, F_SETFL, flags) != 0) { -#endif + msg_perr_strerror("Could not reset serial port mode: "); return -1; } +#endif return ret; }

6 years, 1 month

2
2
0 0

[PATCH] CID1130010: Resource leak

by Stefan Reinauer

CID1130010: Resource leak The system resource will not be reclaimed and reused, reducing the future availability of the resource. In verify_range: Leak of memory or pointers to system resources Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Index: flashrom.c =================================================================== --- flashrom.c (revision 1763) +++ flashrom.c (working copy) @@ -676,7 +676,8 @@ if (!flash->chip->read) { msg_cerr("ERROR: flashrom has no read function for this flash chip.\n"); - return 1; + ret = -1; + goto out_free; } if (!readbuf) { msg_gerr("Could not allocate memory!\n");

6 years, 1 month

2
2
0 0

Detection of MS-7094 as MS-6702E

by Stelios Tsampas

Flashrom detects MS-7094 (http://www.msi.com/product/mb/K8T-Neo2-F-V2-0.html) as MS-6702E (http://www.msi.com/product/mb/K8T-Neo2-F--FIR.html) Note: flashrom successfully flashed MS-7094 even though it wasn't detected properly but it couldn't flash MS-6702E as it couldn't find a suitable erase command. Edit: Re-attached proper lspci output

6 years, 1 month

2
2
0 0

[PATCH] nicintel_eeprom: New programmer for Intel Nics eeproms

by Ricardo Ribalda Delgado

This patch let you read and write the eeprom on your gigagit nic card. So far it has been tested on the 82580 NIC, but there should be other boards also compatibles. It is a nice substitution for the eeupdate tool. Speed is quite decent root@qt5022:~# time ./flashrom -p nicintel_eeprom:pci=03:00.0 -E flashrom v0.9.7-r1622 on Linux 3.11.0-qtec-standard (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Programmer flash chip "Opaque flash chip" (32 kB, Programmer-specific) on nicintel_eeprom. Erasing and writing flash chip... Erase/write done. real 0m4.699s user 0m4.676s sys 0m0.024s root@qt5022:~# time ./flashrom -p nicintel_eeprom:pci=03:00.0 -w original.kk flashrom v0.9.7-r1622 on Linux 3.11.0-qtec-standard (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Programmer flash chip "Opaque flash chip" (32 kB, Programmer-specific) on nicintel_eeprom. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. real 0m3.533s user 0m3.516s sys 0m0.018s Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- Makefile | 9 ++ flashrom.c | 12 ++ nicintel_eeprom.c | 329 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ programmer.h | 9 ++ 4 files changed, 359 insertions(+) create mode 100644 nicintel_eeprom.c diff --git a/Makefile b/Makefile index 70ef640..e9d5fbf 100644 --- a/Makefile +++ b/Makefile @@ -396,6 +396,9 @@ CONFIG_NICINTEL ?= yes # Always enable SPI on Intel NICs for now. CONFIG_NICINTEL_SPI ?= yes +# Always enable EEPROM on Intel NICs for now. +CONFIG_NICINTEL_EEPROM ?= yes + # Always enable SPI on OGP cards for now. CONFIG_OGP_SPI ?= yes @@ -560,6 +563,12 @@ PROGRAMMER_OBJS += nicintel_spi.o NEED_PCI := yes endif +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) +FEATURE_CFLAGS += -D'CONFIG_NICINTEL_EEPROM=1' +PROGRAMMER_OBJS += nicintel_eeprom.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_OGP_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_OGP_SPI=1' PROGRAMMER_OBJS += ogp_spi.o diff --git a/flashrom.c b/flashrom.c index a00347e..0cb948b 100644 --- a/flashrom.c +++ b/flashrom.c @@ -273,6 +273,18 @@ const struct programmer_entry programmer_table[] = { }, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + { + .name = "nicintel_eeprom", + .type = PCI, + .devs.dev = nics_intel_ee, + .init = nicintel_ee_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_OGP_SPI == 1 { .name = "ogp_spi", diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c new file mode 100644 index 0000000..9719c24 --- /dev/null +++ b/nicintel_eeprom.c @@ -0,0 +1,329 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2013 Ricardo Ribalda - Qtechnology A/S + * + * Based on nicinctel_spi.c and ichspi.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Datasheet: Intel 82580 Quad/Dual Gigabit Ethernet LAN Controller Datasheet + */ + +#include <stdlib.h> +#include <unistd.h> +#include "flash.h" +#include "programmer.h" +#include "hwaccess.h" + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define MEMMAP_SIZE getpagesize() + +/* EEPROM/Flash Control & Data Register */ +#define EECD 0x10 +#define EERD 0x14 + +/* Eeprom Access register bits +* Section 8.4.1 +*/ +#define EE_SCK 0 +#define EE_CS 1 +#define EE_SI 2 +#define EE_SO 3 +#define EE_REQ 6 +#define EE_GNT 7 +#define EE_PRES 8 +#define EE_SIZE 11 +#define EE_SIZE_MASK 0xf + +#define EERD_START 0 +#define EERD_DONE 1 +#define EERD_ADDR 2 +#define EERD_DATA 16 + +#define BIT(x) (1<<x) +#define PAGE_MASK 0x3f + +uint8_t *nicintel_eebar; +struct pci_dev *nicintel_pci; + +#define UNPROG_DEVICE 0x1509 + +const struct dev_entry nics_intel_ee[] = { + {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", "82580 Quad/Dual Gigabit Ethernet LAN Controller"}, + {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet LAN Controller"}, + {0}, +}; + +static int nicintel_ee_probe(struct flashctx *flash) +{ + if (nicintel_pci->device_id == UNPROG_DEVICE) + flash->chip->total_size = 16; + else{ + uint32_t tmp; + tmp = pci_mmio_readl(nicintel_eebar + EECD); + tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK); + switch (tmp) { + case 7: + flash->chip->total_size = 16; + break; + case 8: + flash->chip->total_size = 32; + break; + default: + msg_cerr("Non supported chip size 0x%x\n", tmp); + return 0; + } + } + + flash->chip->page_size = PAGE_MASK + 1; + flash->chip->tested = TEST_OK_PREW; + flash->chip->gran = write_gran_1byte; + flash->chip->block_erasers->eraseblocks[0].size = (PAGE_MASK + 1); + flash->chip->block_erasers->eraseblocks[0].count = + (flash->chip->total_size * 1024) / (PAGE_MASK + 1); + + return 1; +} + +#define RETRIES_EERD 10000000 +static int nicintel_ee_read_word(unsigned int daddr, uint16_t * word) +{ + uint32_t tmp; + int i; + + tmp = BIT(EERD_START) + (daddr << EERD_ADDR); + pci_mmio_writel(tmp, nicintel_eebar + EERD); + + for (i = 0; i < RETRIES_EERD; i++) { + tmp = pci_mmio_readl(nicintel_eebar + EERD); + if (tmp & BIT(EERD_DONE)) { + *word = (tmp >> EERD_DATA) & 0xffff; + return 0; + } + } + + return -1; +} + +static int nicintel_ee_read(struct flashctx *flash, uint8_t * buf, + unsigned int addr, unsigned int len) +{ + uint16_t word; + + if (addr & 1) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + } + + while (len) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + if (len) { + *buf++ = (word >> 8) & 0xff; + addr++; + len--; + } + } + + return 0; +} + +static int nicintel_ee_bitset(int reg, int bit, int val) +{ + uint32_t tmp; + + tmp = pci_mmio_readl(nicintel_eebar + reg); + if (val) + tmp |= BIT(bit); + else + tmp &= ~BIT(bit); + pci_mmio_writel(tmp, nicintel_eebar + reg); + + return -1; +} + +static int nicintel_ee_byte(uint8_t mosi, uint8_t * miso) +{ + int i; + uint8_t out = 0x0; + + for (i = 7; i >= 0; i--) { + nicintel_ee_bitset(EECD, EE_SI, mosi & BIT(i)); + nicintel_ee_bitset(EECD, EE_SCK, 1); + if (miso) { + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EECD); + if (tmp & BIT(EE_SO)) + out |= BIT(i); + } + nicintel_ee_bitset(EECD, EE_SCK, 0); + } + + if (miso) + *miso = out; + + return 0; +} + +#define OPCODE_RDSR 0x5 +#define RETRIES_RDSR 100 +#define RDSR_WIP 0 +static int nicintel_ee_ready() +{ + int i; + uint8_t rdsr; + + nicintel_ee_bitset(EECD, EE_CS, 0); + nicintel_ee_byte(OPCODE_RDSR, NULL); + for (i = 0; i < RETRIES_RDSR; i++) { + nicintel_ee_byte(0x00, &rdsr); + if (!(rdsr & BIT(RDSR_WIP))) { + nicintel_ee_bitset(EECD, EE_CS, 1); + programmer_delay(1); + return 0; + } + } + + nicintel_ee_bitset(EECD, EE_CS, 1); + programmer_delay(1); + + return -1; +} + +static int nicintel_ee_req() +{ + uint32_t tmp; + nicintel_ee_bitset(EECD, EE_REQ, 1); + + tmp = pci_mmio_readl(nicintel_eebar + EECD); + if (!(tmp & BIT(EE_GNT))) { + msg_perr("Enabling eeprom access failed.\n"); + return 1; + } + + nicintel_ee_bitset(EECD, EE_SCK, 0); + return 0; +} + +#define DELAY_WRITE 1000 +#define OPCODE_WRITE 0x2 +#define OPCODE_WREN 0x6 +static int nicintel_ee_write(struct flashctx *flash, uint8_t * buf, + unsigned int addr, unsigned int len) +{ + if (nicintel_ee_req()) + return -1; + + if (nicintel_ee_ready()) { + nicintel_ee_bitset(EECD, EE_REQ, 0); + return -1; + } + + while (len) { + //wren + nicintel_ee_bitset(EECD, EE_CS, 0); + nicintel_ee_byte(OPCODE_WREN, NULL); + nicintel_ee_bitset(EECD, EE_CS, 1); + programmer_delay(1); + + //data + nicintel_ee_bitset(EECD, EE_CS, 0); + nicintel_ee_byte(OPCODE_WRITE, NULL); + nicintel_ee_byte((addr >> 8) & 0xff, NULL); + nicintel_ee_byte(addr & 0xff, NULL); + while (len) { + nicintel_ee_byte((buf) ? *buf++ : 0xff, NULL); + len--; + addr++; + if (!(addr & PAGE_MASK)) + break; + } + nicintel_ee_bitset(EECD, EE_CS, 1); + programmer_delay(1); + if (nicintel_ee_ready()) { + nicintel_ee_bitset(EECD, EE_REQ, 0); + return -1; + } + } + + nicintel_ee_bitset(EECD, EE_REQ, 0); + return 0; +} + +static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, + unsigned int len) +{ + return nicintel_ee_write(flash, NULL, addr, len); +} + +static const struct opaque_programmer opaque_programmer_nicintel_ee = { + .probe = nicintel_ee_probe, + .read = nicintel_ee_read, + .write = nicintel_ee_write, + .erase = nicintel_ee_erase, +}; + +static int nicintel_spi_shutdown(void *data) +{ + + /* See the comment about EECD in nicintel_ee_init() for details. */ + + return 0; +} + +int nicintel_ee_init(void) +{ + struct pci_dev *dev = NULL; + uint32_t tmp; + + if (rget_io_perms()) + return 1; + + dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; + + io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", + io_base_addr, MEMMAP_SIZE); + nicintel_pci=dev; + /* Automatic restore of EECD on shutdown is not possible because EECD + * does not only contain EE_REQ but other bits with side effects as well. + * Those other bits must be left untouched. + */ + if (dev->device_id != UNPROG_DEVICE) { + tmp = pci_mmio_readl(nicintel_eebar + EECD); + + if (!(tmp & BIT(EE_PRES))) { + msg_perr("EEprom not present.\n"); + return 1; + } + } + + if (register_shutdown(nicintel_spi_shutdown, NULL)) + return 1; + + return register_opaque_programmer(&opaque_programmer_nicintel_ee); +} diff --git a/programmer.h b/programmer.h index f792d9a..dcf9911 100644 --- a/programmer.h +++ b/programmer.h @@ -78,6 +78,9 @@ enum programmer { #if CONFIG_NICINTEL_SPI == 1 PROGRAMMER_NICINTEL_SPI, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + PROGRAMMER_NICINTEL_EEPROM, +#endif #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI, #endif @@ -406,6 +409,12 @@ int nicintel_spi_init(void); extern const struct dev_entry nics_intel_spi[]; #endif +/* nicintel_eeprom.c */ +#if CONFIG_NICINTEL_EEPROM == 1 +int nicintel_ee_init(void); +extern const struct dev_entry nics_intel_ee[]; +#endif + /* ogp_spi.c */ #if CONFIG_OGP_SPI == 1 int ogp_spi_init(void); -- 1.8.4.rc3

6 years, 2 months

2
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Re: [flashrom] [PATCH] dummyflasher.c: add an "empty" parameter and initialize with random bytes by default

by Carl-Daniel Hailfinger

Am 21.07.2011 17:54 schrieb Stefan Tauner: > previously the dummies were initialized to be empty (all ones), which makes writes skip > erasing altogether. with this patch the default is to fill it with random bytes instead and the > old behavior can be enforced with stating "empty=yes" on the command line. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Does the following not work for you? dd if=/dev/urandom bs=1k count=4k of=oldimage.bin flashrom -p dummy:emulate=SST25VF032B,image=oldimage.bin -w newimage.bin Regards, Carl-Daniel -- http://www.hailfinger.org/

6 years, 2 months

5
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Re: [flashrom] [PATCH] Reorganize shutting down.

by Stefan Tauner

On Fri, 30 Aug 2013 02:00:34 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > This was mainly driven by getting rid of cli_classic_abort_usage() in cli_classic.c. I forgot to mention something and give a rationale for it: Thereby we also get rid of teasing the user to run flashrom again to show usage information. If we think the user should see the usage information we should show it to him or at least a short syntax summary (which we pretty much lack currently: the programmer parameter syntax is not really well explained). (Small) GNU apps seem to favor printing a similar message like we do. nmap, rsync give their whole usage information which is a bit of a pain because it is so long (unlike flashrom's), ping and hd are examples that just print a syntax summary (but they lack a complete usage help). All of the above is stupid. :P Printing a wall of text does not help and is even counterproductive if one can not scroll. Printing how to print help is also a little bit silly if that help text is not very long anyway. The right™ thing in the case of flashrom is IMHO to print the complete usage help (after improving it to explain the programmer parameter syntax better). RFC. > > This makes the whole main function more consistent and fixes a myriad of > (theoretical) memory leaks. This slightly changes output in most error cases. > doit() stops calling programmer_shutdown() with this patch, beware. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

6 years, 2 months

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issue with Micron N25Q128

by Shih-Chieh Huang

Hi, I am having problem programing N25Q128 using flashrom0.9.7. I got the following errors from erasing address at 0x83f000. I have tried different boards and they failed at the same locations. There are three versions of N25Q128, uniform, top, and bottom. Only the 8 first/last sectors of top/bottom version supports subsector erase. But, from N25Q128 configuration in flashchip.c, it first tries SSE (0x20) for the entire chip. Could it be the problem? Is there a fix for this? Thank you very much. Found Micron/Numonyx/ST flash chip "N25Q128..3E" (16384 kB, SPI). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Block protection is disabled. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0..... <skip some subsector erase messages..... > 0x774000-0x774fff:S, 0x775000-0x775fff:S, 0x776000-0x776fff:S, 0x777000-0x777fff:S, 0x778000-0x778fff:S, 0x779000-0x779fff:S, 0x77a000-0x77afff:S, 0x77b000-0x77bfff:S, 0x77c000-0x77cfff:S, 0x77d000-0x77dfff:S, 0x77e000-0x77efff:S, 0x77f000-0x77ffff:S, 0x780000-0x780fff:S, 0x781000-0x781fff:S, 0x782000-0x782fff:S, 0x783000-0x783fff:S, 0x784000-0x784fff:S, 0x785000-0x785fff:S, 0x786000-0x786fff:S, 0x787000-0x787fff:S, 0x788000-0x788fff:S, 0x789000-0x789fff:S, 0x78a000-0x78afff:S, 0x78b000-0x78bfff:S, 0x78c000-0x78cfff:S, 0x78d000-0x78dfff:S, 0x78e000-0x78efff:S, 0x78f000-0x78ffff:S, 0x790000-0x790fff:S, 0x791000-0x791fff:S, 0x792000-0x792fff:S, 0x793000-0x793fff:S, 0x794000-0x794fff:S, 0x795000-0x795fff:S, 0x796000-0x796fff:S, 0x797000-0x797fff:S, 0x798000-0x798fff:S, 0x799000-0x799fff:S, 0x79a000-0x79afff:S, 0x79b000-0x79bfff:S, 0x79c000-0x79cfff:S, 0x79d000-0x79dfff:S, 0x79e000-0x79efff:S, 0x79f000-0x79ffff:S, 0x7a0000-0x7a0fff:S, 0x7a1000-0x7a0 (payload length was 64). spi_nbyte_program failed during command execution at address 0x83f000 Reading current flash chip contents... done. Looking for another erase function. Trying erase function 1... 0x000000-0x00ffff:S, 0x010000-0x01ffff:S, 0x020000-0x02ffff:S, 0x030000-0x03ffff:S, 0x040000-0x04ffff:S, 0x050000-0x05ffff:S, 0x060000-0x06ffff:S, 0x070000-0x07ffff:S, 0x080000-0x08ffff:S, 0x090000-0x09ffff:S, 0x0a0000-0x0affff:S, 0x0b0000-0x0bffff:S, 0x0c0000-0x0cffff:S, 0x0d0000-0x0dffff:S, 0x0e0000-0x0effff:S, 0x0f0000-0x0fffff:S, 0x100000-0x10ffff:S, 0x110000-0x11ffff:S, 0x120000-0x12ffff:S, 0x130000-0x13ffff:S, 0x140000-0x14ffff:S, 0x150000-0x15ffff:S, 0x160000-0x16ffff:S, 0x170000-0x17ffff:S, 0x180000-0x18ffff:S, 0x190000-0x19ffff:S, 0x1a0000-0x1affff:S, 0x1b0000-0x1bffff:S, 0x1c0000-0x1cffff:S, 0x1d0000-0x1dffff:S, 0x1e0000-0x1effff:S, 0x1f0000-0x1fffff:S, 0x200000-0x20ffff:S, 0x210000-0x21ffff:S, 0x220000-0x22ffff:S, 0x230000-0x23ffff:S, 0x240000-0x24ffff:S, 0x250000-0x25ffff:S, 0x260000-0x26ffff:S, 0x270000-0x27ffff:S, 0x280000-0x28ffff:S, 0x290000-0x29ffff:S, 0x2a0000-0x2affff:S, 0x2b0000-0x2bffff:S, 0x2c0000-0x2cffff:S, 0x2d0000-0x2dffff:S, 0x2e0000-0x2effff:S, 0x2f0000-0x2fffff:S, 0x300000-0x30ffff:S, 0x310000-0x31ffff:S, 0x320000-0x32ffff:S, 0x330000-0x33ffff:S, 0x340000-0x34ffff:S, 0x350000-0x35ffff:S, 0x360000-0x36ffff:S, 0x370000-0x37ffff:S, 0x380000-0x38ffff:S, 0x390000-0x39ffff:S, 0x3a0000-0x3affff:S, 0x3b0000-0x3bffff:S, 0x3c0000-0x3cffff:S, 0x3d0000-0x3dffff:S, 0x3e0000-0x3effff:S, 0x3f0000-0x3fffff:S, 0x400000-0x40ffff:S, 0x410000-0x41ffff:S, 0x420000-0x42ffff:S, 0x430000-0x43ffff:S, 0x440000-0x44ffff:S, 0x450000-0x45ffff:S, 0x460000-0x46ffff:S, 0x470000-0x47ffff:S, 0x480000-0x48ffff:S, 0x490000-0x49ffff:S, 0x4a0000-0x4affff:S, 0x4b0000-0x4bffff:S, 0x4c0000-0x4cffff:S, 0x4d0000-0x4dffff:S, 0x4e0000-0x4effff:S, 0x4f0000-0x4fffff:S, 0x500000-0x50ffff:S, 0x510000-0x51ffff:S, 0x520000-0x52ffff:S, 0x530000-0x53ffff:S, 0x540000-0x54ffff:S, 0x550000-0x55ffff:S, 0x560000-0x56ffff:S, 0x570000-0x57ffff:S, 0x580000-0x58ffff:S, 0x590000-0x59ffff:S, 0x5a0000-0x5affff:S, 0x5b0000-0x5bffff:S, 0x5c0000-0x5cffff:S, 0x5d0000-0x5dffff:S, 0x5e0000-0x5effff:S, 0x5f0000-0x5fffff:S, 0x600000-0x60ffff:S, 0x610000-0x61ffff:S, 0x620000-0x62ffff:S, 0x630000-0x63ffff:S, 0x640000-0x64ffff:S, 0x650000-0x65ffff:S, 0x660000-0x66ffff:S, 0x670000-0x67ffff:S, 0x680000-0x68ffff:S, 0x690000-0x69ffff:S, 0x6a0000-0x6affff:S, 0x6b0000-0x6bffff:S, 0x6c0000-0x6cffff:S, 0x6d0000-0x6dffff:S, 0x6e0000-0x6effff:S, 0x6f0000-0x6fffff:S, 0x700000-0x70ffff:S, 0x710000-0x71ffff:S, 0x720000-0x72ffff:S, 0x730000-0x73ffff:S, 0x740000-0x74ffff:S, 0x750000-0x75ffff:S, 0x760000-0x76ffff:S, 0x770000-0x77ffff:S, 0x780000-0x78ffff:S, 0x790000-0x79ffff:S, 0x7a0000-0x7affff:S, 0x7b0000-0x7bffff:S, 0x7c0000-0x7cffff:S, 0x7d0000-0x7dffff:S, 0x7e0000-0x7effff:S, 0x7f0000-0x7fffff:S, 0x800000-0x80ffff:S, 0x810000-0x81ffff:S, 0x820000-0x82ffff:S, 0x830000-0x83ffff:WTransaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=1, SPOP=0, COP=0, DBC=63, SME=0, SCF=0 Running OPCODE 0x02 failed at address 0x83f000 (payload length was 64). spi_nbyte_program failed during command execution at address 0x83f000 Reading current flash chip contents... done. Looking for another erase function. Trying erase function 2... 0x000000-0xffffff:WTransaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=1, SPOP=0, COP=0, DBC=63, SME=0, SCF=0 Running OPCODE 0x02 failed at address 0x83f000 (payload length was 64). spi_nbyte_program failed during command execution at address 0x83f000 Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything changed. Good. It seems nothing was changed. Writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks! ------------------------------------------------------------------------------- You may now reboot or simply leave the machine running. Restoring MMIO space at 0x7ff240f028a0 Restoring MMIO space at 0x7ff240f0289c Restoring MMIO space at 0x7ff240f02898 Restoring MMIO space at 0x7ff240f02896 Restoring MMIO space at 0x7ff240f02894 flashchips.c: { .vendor = "Micron/Numonyx/ST", .name = "N25Q128..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = ST_N25Q128__3E, .total_size = 16384, .page_size = 256, /* supports SFDP */ /* OTP: 64B total; read 0x4B, write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { .eraseblocks = { {4 * 1024, 4096 } }, .block_erase = spi_block_erase_20, }, { .eraseblocks = { {64 * 1024, 256} }, .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {16384 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, Thanks, Cliff

6 years, 2 months

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flashrom -V of Acer EM61SM/EM61PM (Desktop)

by Benjamin Bellec

Hello, I succesfully flash the BIOS of an Acer Aspire T180 Desktop. Chipset seems to be Nvidia MCP61. At first reboot, motherboard doesn't boot and beep. I had to clear CMOS and then it's OK. As requested by flashrom, here is the flashrom -V : flashrom v0.9.6.1-r1705 on Linux 3.9.5-301.fc19.x86_64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.0, GCC 4.8.1 20130603 (Red Hat 4.8.1-1), little endian Command line (1 args): flashrom -V Using default programmer "internal". Calibrating delay loop... OS timer resolution is 1 usecs, 531M loops per second, 10 myus = 11 us, 100 myus = 107 us, 1000 myus = 999 us, 10000 myus = 9976 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Acer" DMI string system-product-name: "Aspire T180" DMI string system-version: "R01-A2" DMI string baseboard-manufacturer: "Acer" DMI string baseboard-product-name: "EM61SM/EM61PM " DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8726 on port 0x2e Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0x00000000 MCP SPI is not used. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. Super I/O ID 0x8726 is not on the list of flash capable controllers. The following protocols are supported: LPC. Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x27, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Found SST flash chip "SST49LF040B" (512 kB, LPC) at physical address 0xfff80000. Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 Found SST flash chip "SST49LF040B" (512 kB, LPC). No operations were specified. Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x90 Restoring PCI config space for 00:01:0 reg 0x8c Restoring PCI config space for 00:01:0 reg 0x88

6 years, 2 months

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flashrom December 2013