flashrom December 2013

flashrom@flashrom.org

24 participants
69 discussions

[PATCH] CID1130006: Resource leak
by Stefan Reinauer 26 Apr '14

26 Apr '14

CID1130006: Resource leak The system resource will not be reclaimed and reused, reducing the future availability of the resource. In buspirate_spi_init: Leak of memory or pointers to system resources Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Index: buspirate_spi.c =================================================================== --- buspirate_spi.c (revision 1763) +++ buspirate_spi.c (working copy) @@ -250,6 +250,7 @@ if (!bp_commbuf) { bp_commbufsize = 0; msg_perr("Out of memory!\n"); + free(dev); return ERROR_OOM; } bp_commbufsize = DEFAULT_BUFSIZE;

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[PATCH] CID1130002: Logically dead code
by Stefan Reinauer 26 Apr '14

26 Apr '14

CID1130002: Logically dead code The indicated dead code may have performed some action; that action will never occur. In satamv_init: Code can never be reached because of a logical contradiction What we really want to do is check whether PCI_BASE_ADDRESS_2 is valid at this point, and not PCI_BASE_ADDRESS_0. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Index: satamv.c =================================================================== --- satamv.c (revision 1763) +++ satamv.c (working copy) @@ -139,7 +139,7 @@ /* Get I/O BAR location. */ tmp = pcidev_readbar(dev, PCI_BASE_ADDRESS_2); - if (!addr) + if (!tmp) return 1; /* Truncate to reachable range.

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[PATCH] Refactor spi_read_status_register usage
by Carl-Daniel Hailfinger 08 Mar '14

08 Mar '14

spi_read_status_register() is used in open-coded loops everywhere just to check if SPI_SR_WIP bit cleared. The logic is missing a timeout detection, and we can save quite a lot of code by introducing a function which waits until SPI_SR_WIP is cleared or a timeout is reached. Untested. May explode. Unfinished. More functions need to be converted to the new style. Will change behaviour if the chip is too slow or hangs. Should prevent flashrom from hanging without any visible output. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_rdsr_refactor/spi25.c =================================================================== --- flashrom-spi_rdsr_refactor/spi25.c (Revision 1653) +++ flashrom-spi_rdsr_refactor/spi25.c (Arbeitskopie) @@ -328,14 +328,9 @@ __func__); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 1-85 s, so wait in 1 s steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1000 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 120 * 1000 * 1000, JEDEC_CE_60); + return result; } int spi_chip_erase_62(struct flashctx *flash) @@ -365,14 +360,9 @@ __func__); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 2-5 s, so wait in 100 ms steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 120 * 1000 * 1000, JEDEC_CE_62); + return result; } int spi_chip_erase_c7(struct flashctx *flash) @@ -401,14 +391,9 @@ msg_cerr("%s failed during command execution\n", __func__); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 1-85 s, so wait in 1 s steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1000 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 120 * 1000 * 1000, JEDEC_CE_C7); + return result; } int spi_block_erase_52(struct flashctx *flash, unsigned int addr, @@ -444,13 +429,9 @@ __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_BE_52); + return result; } /* Block size is usually @@ -491,13 +472,9 @@ __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_BE_D8); + return result; } /* Block size is usually @@ -536,13 +513,9 @@ __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_BE_D7); + return result; } /* Sector size is usually 4k, though Macronix eliteflash has 64k */ @@ -579,13 +552,9 @@ __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 15-800 ms, so wait in 10 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(10 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_SE); + return result; } int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen) @@ -619,13 +588,9 @@ msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 10 ms, so wait in 1 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_BE_50); + return result; } int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen) @@ -659,13 +624,9 @@ msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); return result; } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 8 ms, so wait in 1 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1 * 1000); /* FIXME: Check the status register for errors. */ - return 0; + result = spi_wait_status_register_ready(flash, 10 * 1000 * 1000, JEDEC_BE_81); + return result; } int spi_block_erase_60(struct flashctx *flash, unsigned int addr, Index: flashrom-spi_rdsr_refactor/spi25_statusreg.c =================================================================== --- flashrom-spi_rdsr_refactor/spi25_statusreg.c (Revision 1653) +++ flashrom-spi_rdsr_refactor/spi25_statusreg.c (Arbeitskopie) @@ -43,7 +43,6 @@ static int spi_write_status_register_flag(struct flashctx *flash, int status, const unsigned char enable_opcode) { int result; - int i = 0; /* * WRSR requires either EWSR or WREN depending on chip type. * The code below relies on the fact hat EWSR and WREN have the same @@ -78,17 +77,10 @@ /* WRSR performs a self-timed erase before the changes take effect. * This may take 50-85 ms in most cases, and some chips apparently * allow running RDSR only once. Therefore pick an initial delay of - * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed. + * 100 ms, then wait until a total of 5 s have elapsed. */ programmer_delay(100 * 1000); - while (spi_read_status_register(flash) & SPI_SR_WIP) { - if (++i > 490) { - msg_cerr("Error: WIP bit after WRSR never cleared\n"); - return TIMEOUT_ERROR; - } - programmer_delay(10 * 1000); - } - return 0; + return spi_wait_status_register_ready(flash, 4900 * 1000, JEDEC_WRSR); } int spi_write_status_register(struct flashctx *flash, int status) @@ -108,6 +100,28 @@ return ret; } +/* timeout is specified in usecs. */ +int spi_wait_status_register_ready(struct flashctx *flash, int timeout, uint8_t opcode) +{ + /* At least 1 usec between iterations. */ + int single_delay = (timeout / 100) ? : 1; + int elapsed = 0; + int halftime = 0; + + while (spi_read_status_register(flash) & SPI_SR_WIP) { + elapsed += single_delay; + if ((elapsed > timeout / 2) && !halftime) { + msg_cdbg("Debug: WIP bit after %02x didn't clear within %i us.\n", opcode, timeout/2); + } + if (elapsed >= timeout) { + msg_cerr("Error: WIP bit after %02x didn't clear within %i us.\n", opcode, timeout); + return TIMEOUT_ERROR; + } + programmer_delay(single_delay); + } + return 0; +} + uint8_t spi_read_status_register(struct flashctx *flash) { static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; Index: flashrom-spi_rdsr_refactor/chipdrivers.h =================================================================== --- flashrom-spi_rdsr_refactor/chipdrivers.h (Revision 1653) +++ flashrom-spi_rdsr_refactor/chipdrivers.h (Arbeitskopie) @@ -60,6 +60,7 @@ /* spi25_statusreg.c */ uint8_t spi_read_status_register(struct flashctx *flash); +int spi_wait_status_register_ready(struct flashctx *flash, int timeout, uint8_t opcode); int spi_write_status_register(struct flashctx *flash, int status); int spi_prettyprint_status_register_plain(struct flashctx *flash); int spi_prettyprint_status_register_default_bp1(struct flashctx *flash); -- http://www.hailfinger.org/

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how to flashrom on alix 2d3 boards?
by d l f 31 Dec '13

31 Dec '13

Hello , I am interesting flashrom tool , and saw the site mentioned the tool is compatible with pc engines alix 2d3. http://www.flashrom.org/Supported_hardware but this boards without vga output ,and only has a serial port to check the board status. could you tell me how to step by step flash bios ? Thanks, deng 2013-12-31

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Supermicro X6DVL-EG2 results
by Jared Mauch 31 Dec '13

31 Dec '13

[root@nat flashrom]# ./flashrom -p internal -Vw ~jared/6eg21257.rom flashrom v0.9.7-r1764 on Linux 2.6.32-358.18.1.el6.x86_64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.10, GCC 4.4.7 20120313 (Red Hat 4.4.7-3), little endian Command line (4 args): ./flashrom -p internal -Vw /home/jared/6eg21257.rom Calibrating delay loop... OS timer resolution is 1 usecs, 1635M loops per second, 10 myus = 18 us, 100 myus = 98 us, 1000 myus = 983 us, 10000 myus = 9438 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Desktop" DMI string system-manufacturer: "Supermicro" DMI string system-product-name: "X6DVL-EG2" DMI string system-version: "1234567890" DMI string baseboard-manufacturer: "Supermicro" DMI string baseboard-product-name: "X6DVL-EG2" DMI string baseboard-version: "1234567890" Found Winbond Super I/O, id 0x52 W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 00. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found chipset "Intel 6300ESB" with PCI ID 8086:25a1. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled OK. The following protocols are supported: FWH. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x89, id2 0xac Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x89, id2 0xac Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x89, id2 0xac Found Intel flash chip "82802AC" (1024 kB, FWH) at physical address 0xfff00000. Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x89, id2 0xac Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x89, id2 0xac Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x89, id2 0xac Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x89, id2 0xac Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x89, id2 0xac Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x89, id2 0xac Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x89, id2 0xac Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x89, id2 0xac Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x89, id2 0xac Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x89, id2 0xac Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x89, id2 0xac Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x89, id2 0xac Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x89, id2 0xac Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x89, id2 0xac Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x89, id2 0xac Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x89, id2 0xac Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x89, id2 0xac Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x89, id2 0xac Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x89, id2 0xac Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x89, id2 0xac Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x89, id2 0xac Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x89, id2 0xac Found Intel flash chip "82802AC" (1024 kB, FWH). === This flash part has status UNTESTED for operations: ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -VE, -Vw), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x00ffff:S, 0x010000-0x01ffff:S, 0x020000-0x02ffff:S, 0x030000-0x03ffff:S, 0x040000-0x04ffff:S, 0x050000-0x05ffff:S, 0x060000-0x06ffff:S, 0x070000-0x07ffff:S, 0x080000-0x08ffff:S, 0x090000-0x09ffff:S, 0x0a0000-0x0affff:S, 0x0b0000-0x0bffff:S, 0x0c0000-0x0cffff:S, 0x0d0000-0x0dffff:S, 0x0e0000-0x0effff:EReady:BE RUN/FINISH:BE ERROR:PROG OK:VPP OK:PROG RUN/FINISH:WP|TBL#|WP#,ABORT:FAILED at 0x000ec000! Expected=0xff, Found=0x07, failed byte count from 0x000e0000-0x000effff: 0x11ef ERASE FAILED! Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything changed. Good. It seems nothing was changed. Writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks! ------------------------------------------------------------------------------- You may now reboot or simply leave the machine running. Restoring PCI config space for 00:1f:0 reg 0x4e

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Flashrom report/DELL Optiplex 980
by William Voccia 30 Dec '13

30 Dec '13

Hello, I've attached a verbose Flashrom report for a Dell Optiplex 980 I'm trying to flash. thank you. flashrom v0.9.6.1-r1563 on Linux 3.8.0-19-generic (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.9, GCC 4.7.1, little endian Command line (5 args): flashrom -V -w O980-A09.hdr --programmer internal Calibrating delay loop... OS timer resolution is 1 usecs, 1679M loops per second, 10 myus = 10 us, 100 myus = 104 us, 1000 myus = 976 us, 10000 myus = 10145 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Dell Inc." DMI string system-product-name: "OptiPlex 980 " DMI string system-version: "Not Specified" DMI string baseboard-manufacturer: "Dell Inc." DMI string baseboard-product-name: "0D441T" DMI string baseboard-version: "A01" DMI string chassis-type: "Mini Tower" Found chipset "Intel Q57" with PCI ID 8086:3b0a. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x0 0xffe00000/0xffa00000 FWH IDSEL: 0x0 0xffd80000/0xff980000 FWH IDSEL: 0x0 0xffd00000/0xff900000 FWH IDSEL: 0x0 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x300000 bytes BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2 WARNING: Setting 0xdc from 0x2 to 0x3 on Q57 failed. New value is 0x2. Root Complex Register Block address = 0xfeda8000 GCS = 0xc61: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfeda8000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x09ff0700 FREG1: BIOS region (0x00700000-0x009fffff) is read-write. 0x5C: 0x06ff0023 FREG2: WARNING: Management Engine region (0x00023000-0x006fffff) is locked. 0x60: 0x00220021 FREG3: Gigabit Ethernet region (0x00021000-0x00022fff) is read-write. 0x64: 0x00200001 FREG4: WARNING: Platform Data region (0x00001000-0x00020fff) is locked. Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled. You can enforce write support with the ich_spi_force programmer option, but it will most likely harm your hardware! If you force flashrom you will get no support if something breaks. 0x90: 0x04 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf84054 (SSFC) SSFC: SCGO=0, ACS=1, SPOP=0, COP=5, DBC=0, SME=0, SCF=0 0x94: 0x0606 (PREOP) 0x96: 0x4fc8 (OPTYPE) 0x98: 0x029fabab (OPMENU) 0x9C: 0x01050220 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Enabling hardware sequencing due to multiple flash chips detected. SPI Read Configuration: prefetching disabled, caching enabled, PROBLEMS, continuing anyway The following protocols are supported: FWH, Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found 2 attached SPI flash chips with a combined density of 10240 kB. There is only one partition containing the whole address space (0x000000 - 0x9fffff). There are 2560 erase blocks with 4096 B each. Found Programmer flash chip "Opaque flash chip" (10240 kB, Programmer-specific) at physical address 0x0. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xdc, id2 0x7a, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xdc, id2 0x7a, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Programmer flash chip "Opaque flash chip" (10240 kB, Programmer-specific). Write/erase is not working yet on your programmer in its current configuration. Aborting. Restoring MMIO space at 0x7f27650948a0 Restoring PCI config space for 00:1f:0 reg 0xdc

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Re: [flashrom] Trouble disabling write-protection on Chromebook
by BM-2cWKH3wgq8zXX9eHfba16oTc8b61ead4Yq＠bitmessage.ch 27 Dec '13

27 Dec '13

> Can you try running "flashrom -p host --wp-disable -V" and pasting the > output on paste.flashrom.org? > Here it is: http://paste.flashrom.org/view.php?id=1851 > > If you have a voltmeter handy, you can also try measuring the voltage > on > > > the /WP pin (pin 3). More details on pin configuration can be found in >> the >> > datasheet: >> > >> http://www.winbond-usa.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/… >> > >> >> I don't have voltmeter; I'm sure I could locate one given enough time >> though. Do you have any other suggestions as to steps I might be >> overlooking here? Otherwise, what should I be looking for specifically >> in >> the Winbond data sheet? >> > > Unfortunately I don't have many ideas here... I've only seen this once and > it seemed to be a defective chip since I couldn't change the write-protect > status by removing the chip and using an external programmer. (This was on > a different machine, and not in a retail unit) > > The only reason for failure should be if there is anything bridging the > gap > between the copper pads around the write-protect screw hole, thereby > connecting /WP on the chip to ground. If you have a magnifying glass, can > you inspect just to make sure there is nothing connecting those pads? I took the Chromebook apart and cleaned the area around the write-protect screw hole using alcohol-dabbed q-tips a second time. Visual inspection did not reveal anything that appeared to be joining the two "halves" of the gold screw hole ring. Running "flashrom --wp-disable" as root gave me the same failure message as before, details in the paste. I executed "flashrom -p host --wp-range 0 0" and got this result: flashrom v0.9.4 : 4169bc8 : Sep 21 2013 02:17:24 UTC on Linux 3.4.0 (armv7l), built with libpci 3.1.10, GCC 4.7.x-google 20130114 (prerelease), little endian expected=0xe0, but actual=0xb8. FAILED Then, executing "flashrom -p host --wp-status" gave this result: flashrom v0.9.4 : 4169bc8 : Sep 21 2013 02:17:24 UTC on Linux 3.4.0 (armv7l), built with libpci 3.1.10, GCC 4.7.x-google 20130114 (prerelease), little endian WP: status: 0x00b8 WP: status.srp0: 1 WP: status.srp1: 0 WP: write protect is enabled. WP: write protect range: start=0x00000000, len=0x00200000

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Re: [flashrom] How to program PIIX4 GPO26 for output to make
by Gelip 26 Dec '13

26 Dec '13

Thx for replay :-). I was not sure wher to improve the code, in flashrom, coreboot or maybe seabios. Now I know :-) P.S. I test command 'setpci -s 00:07.0 b2.w=8000' and this also make flashrom working but byte=e0 is from PCI config space table from vendor BIOS. Thanks again, I will seek help on coreboot list.

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Re: [flashrom] How to program PIIX4 GPO26 for output to make
by Gelip 26 Dec '13

26 Dec '13

Also enable program chip like this: (PCI word register b2) setpci -s 00:07.0 b2.w=e000 or (PCI byte register b3) setpci -s 00:07.0 b3.b=e0 e0h = 224DEC = 11100000 binary (bits 5, 6, 7) Please help add or fix code to make flashrom program.

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Re: [flashrom] How to program PIIX4 GPO26 for output to make flashrom
by Gelip 23 Dec '13

23 Dec '13

I think I found how to enable BIOS chip programming. I make dump PCI config space registers device: 00:07.0 Intel Corporation 82371AB/EB/MB PIIX4 ISA [8086:7110] while vendor BIOS and while coreboot bios and compare them. I tried to change the DWORD at offset b0 and flashrom no longer displays an error GPO26 :-) This is log after boot debian on coreboot: ======================================================================================== root@debian:~# flashrom -p internal flashrom v0.9.7-r1763 on Linux 2.6.32-5-486 (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. coreboot table found at 0x9fe1c00. Found chipset "Intel PIIX4/4E/4M". Enabling flash write... OK. Enabling full flash access for board "abit BF6"... ERROR: PIIX4 GPO26 not programmed for output. FAILED! Aborting to be safe. Error: Programmer initialization failed. ======================================================================================== No try set PCI register at offset b0: setpci -s 00:07.0 b0.l=e0000105 and now flashrom working :-): ======================================================================================== root@debian:~# flashrom -p internal flashrom v0.9.7-r1763 on Linux 2.6.32-5-486 (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. coreboot table found at 0x9fe1c00. Found chipset "Intel PIIX4/4E/4M". Enabling flash write... OK. Enabling full flash access for board "abit BF6"... OK. Found Winbond flash chip "W49F002U/N" (256 kB, Parallel) at physical address 0xfffc0000. No operations were specified.

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flashrom December 2013