flashrom July 2011

flashrom@flashrom.org

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275 discussions

[PATCH] Man page fixes: dummy, satamv, it87
by Carl-Daniel Hailfinger 24 Jul '11

24 Jul '11

Man page fixes: - Add dummy programmer flash chip emulation - Add satamv programmer - Merge it87spi programmer into internal section - Correct formatting of pci= parameter Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-manpage_dummy_satamv_it87spi/flashrom.8 =================================================================== --- flashrom-manpage_dummy_satamv_it87spi/flashrom.8 (Revision 1380) +++ flashrom-manpage_dummy_satamv_it87spi/flashrom.8 (Arbeitskopie) @@ -168,7 +168,7 @@ .sp .BR "* internal" " (default, for in-system flashing in the mainboard)" .sp -.BR "* dummy" " (just prints all operations and accesses)" +.BR "* dummy" " (prints all operations and accesses, can emulate flash chips)" .sp .BR "* nic3com" " (for flash ROMs on 3COM network cards)" .sp @@ -192,9 +192,6 @@ .sp .BR "* atahpt" " (for flash ROMs on Highpoint ATA/RAID controllers)" .sp -.BR "* it87spi" " (for flash ROMs behind an ITE IT87xx Super I/O LPC/SPI \ -translation unit)" -.sp .BR "* ft2232_spi" " (for SPI flash ROMs attached to an FT2232/FT4232H family \ based USB SPI programmer)" .sp @@ -286,17 +283,17 @@ .B " flashrom \-p internal:boardmismatch=force" .sp If your mainboard uses an ITE IT87 series Super I/O for LPC<->SPI flash bus -translation, flashrom should autodetect that configuration. You can use the +translation, flashrom should autodetect that configuration. If you want to +set the I/O base port of the IT87 series SPI controller manually instead of +using the value provided by the BIOS, use the .sp .B " flashrom \-p internal:it87spiport=portnum" .sp -syntax as explained in the -.B it87spi -programmer section to use a non-default port for controlling the IT87 series -Super I/O. In the unlikely case flashrom doesn't detect an active -IT87 LPC<->SPI bridge, you can try to force recognition by using the -.B it87spi -programmer. +syntax where +.B portnum +is the I/O port number (must be a multiple of 8). In the unlikely case +flashrom doesn't detect an active IT87 LPC<->SPI bridge, please send a bug +report so we can diagnose the problem. .sp Using flashrom on laptops is dangerous and may easily make your hardware unusable (see also the @@ -322,7 +319,9 @@ .BR "dummy " programmer An optional parameter specifies the bus types it should support. For that you have to use the -.B "flashrom \-p dummy:bus=[type[+type[+type]]]" +.sp +.B " flashrom \-p dummy:bus=[type[+type[+type]]]" +.sp syntax where .B type can be @@ -332,6 +331,51 @@ .sp Example: .B "flashrom \-p dummy:bus=lpc+fwh" +.sp +The dummy programmer supports flash chip emulation for automated self-tests +without hardware access. If you want to emulate a flash chip, use the +.sp +.B " flashrom \-p dummy:emulate=chip" +.sp +syntax where +.B chip +is one of the following chips (please specify only the chip name, not the +vendor): +.sp +.RB "* ST " M25P10.RES " SPI flash chip (RES, page write)" +.sp +.RB "* SST " SST25VF040.REMS " SPI flash chip (REMS, byte write)" +.sp +.RB "* SST " SST25VF032B " SPI flash chip (RDID, AAI write)" +.sp +Example: +.B "flashrom -p dummy:emulate=SST25VF040.REMS" +.sp +If you use flash chip emulation, flash image persistence is available as well +by using the +.sp +.B " flashrom \-p dummy:emulate=chip,image=image.rom" +.sp +syntax where +.B image.rom +is the file where the simulated chip contents are read on flashrom startup and +where the chip contents on flashrom shutdown are written to. +.sp +Example: +.B "flashrom -p dummy:emulate=M25P10.RES,image=dummy.bin" +.sp +If you use SPI flash chip emulation for a chip which supports SPI page write +with the default opcode, you can set the maximum allowed write chunk size with +the +.sp +.B " flashrom \-p dummy:emulate=chip,spi_write_256_chunksize=size" +.sp +syntax where +.B size +is the number of bytes (min. 1, max. 256). +.sp +Example: +.B "flashrom -p dummy:emulate=M25P10.RES,spi_write_256_chunksize=5" .TP .BR "nic3com" , " nicrealtek" , " nicsmc1211" , " nicnatsemi" , " nicintel\ " , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii\ @@ -339,7 +383,9 @@ These programmers have an option to specify the PCI address of the card your want to use, which must be specified if more than one card supported by the selected programmer is installed in your system. The syntax is -.BR "flashrom \-p xxxx:pci=bb:dd.f" , +.sp +.BR " flashrom \-p xxxx:pci=bb:dd.f" , +.sp where .B xxxx is the name of the programmer @@ -353,19 +399,6 @@ Example: .B "flashrom \-p nic3com:pci=05:04.0" .TP -.BR "it87spi " programmer -An optional -.B it87spiport -parameter sets the I/O base port of the IT87 series SPI controller -interface to the port specified in the parameter instead of using the port -address set by the BIOS. For that you have to use the -.sp -.B " flashrom \-p it87spi:it87spiport=portnum" -.sp -syntax where -.B portnum -is an I/O port number which must be a multiple of 8. -.TP .BR "ft2232_spi " programmer An optional parameter specifies the controller type and interface/port it should support. For that you have to use the @@ -487,9 +520,6 @@ needs raw memory access, PCI configuration space access, raw I/O port access (x86) and MSR access (x86). .sp -.B it87spi -needs raw I/O port access (x86). -.sp .BR nic3com ", " nicrealtek ", " nicsmc1211 " and " nicnatsemi " need PCI configuration space read access and raw I/O port access. .sp @@ -505,6 +535,10 @@ .B satasii needs PCI configuration space read access and raw memory access. .sp +.B satamv +needs PCI configuration space read access, raw I/O port access and raw memory +access. +.sp .B serprog needs TCP access to the network or userspace access to a serial port. .sp @@ -517,8 +551,8 @@ .B dummy needs no access permissions at all. .sp -.BR internal ", " it87spi ", " nic3com ", " nicrealtek ", " nicsmc1211 ", " -.BR nicnatsemi ", " "gfxnvidia" ", " drkaiser ", " satasii " and " atahpt +.BR internal ", " nic3com ", " nicrealtek ", " nicsmc1211 ", " nicnatsemi ", " +.BR gfxnvidia" ", " drkaiser ", " satasii ", " satamv " and " atahpt have to be run as superuser/root, and need additional raw access permission. .sp .BR serprog ", " buspirate_spi ", " dediprog " and " ft2232_spi -- http://www.hailfinger.org/

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Asus EEE PC 1201N netbook
by Filatov Sergey Dmitrievich 24 Jul '11

24 Jul '11

flashrom log in attachment. -- Regards, Sergey Filatov

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Gigabyte
by halloaron＠web.de 24 Jul '11

24 Jul '11

http://www.flashrom.org/pipermail/flashrom/2011-July/007348.html Its works. Acked. ___________________________________________________________ Schon gehört? WEB.DE hat einen genialen Phishing-Filter in die Toolbar eingebaut! http://produkte.web.de/go/toolbar

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[PATCH] Add support for the GIGABYTE GA-8SIMLH board.
by Michael Karcher 24 Jul '11

24 Jul '11

The usage of the GPIO output register as bitmap can be confirmed from the vendor board enable code, so the comment has been deleted. It really is (1<<gpionumber). lspci: http://paste.flashrom.org/view.php?id=729 superiotool: http://paste.flashrom.org/view.php?id=730 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 9 +++++---- print.c | 1 + 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/board_enable.c b/board_enable.c index b3dc58e..1a2c108 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1725,12 +1725,13 @@ static int via_apollo_gpo0_lower(void) } /* - * Enable some GPIO pin on SiS southbridge. + * Enable some GPIO pin on SiS southbridge and enables SIO flash writes. * * Suited for: * - MSI 651M-L: SiS651 / SiS962 + * - GIGABYTE GA-8SIMLH */ -static int board_msi_651ml(void) +static int sis_gpio0_raise_and_w836xx_memw(void) { struct pci_dev *dev; uint16_t base, temp; @@ -1741,7 +1742,6 @@ static int board_msi_651ml(void) return 1; } - /* Registers 68 and 64 seem like bitmaps. */ base = pci_read_word(dev, 0x74); temp = INW(base + 0x68); temp &= ~(1 << 0); /* Make pin output? */ @@ -2035,6 +2035,7 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise}, {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, + {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7012, 0x1458, 0xa002, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw}, {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, @@ -2063,7 +2064,7 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise}, - {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, + {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, sis_gpio0_raise_and_w836xx_memw}, {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise}, diff --git a/print.c b/print.c index 0db0339..2cf89f1 100644 --- a/print.c +++ b/print.c @@ -532,6 +532,7 @@ const struct board_info boards_known[] = { B("GIGABYTE", "GA-7ZM", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1366", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option."), B("GIGABYTE", "GA-8IP775", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1830", NULL), B("GIGABYTE", "GA-8IRML", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1343", NULL), + B("GIGABYTE", "GA-8SIMLH", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1399", NULL), B("GIGABYTE", "GA-8PE667 Ultra 2", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1607", NULL), B("GIGABYTE", "GA-965GM-S2 (rev. 2.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2617", NULL), B("GIGABYTE", "GA-965P-DS4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2288", NULL), -- 1.7.5.4

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[commit] r1383 - trunk
by repository service 24 Jul '11

24 Jul '11

Author: hailfinger Date: Sun Jul 24 20:41:13 2011 New Revision: 1383 URL: http://flashrom.org/trac/flashrom/changeset/1383 Log: Man page fixes: - Finish dummy programmer description - Add satamv programmer - Merge it87spi programmer into internal section - Cosmetics Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashrom.8 Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Sun Jul 24 18:30:31 2011 (r1382) +++ trunk/flashrom.8 Sun Jul 24 20:41:13 2011 (r1383) @@ -168,7 +168,7 @@ .sp .BR "* internal" " (default, for in-system flashing in the mainboard)" .sp -.BR "* dummy" " (just prints all operations and accesses)" +.BR "* dummy" " (virtual programmer for testing flashrom)" .sp .BR "* nic3com" " (for flash ROMs on 3COM network cards)" .sp @@ -192,9 +192,6 @@ .sp .BR "* atahpt" " (for flash ROMs on Highpoint ATA/RAID controllers)" .sp -.BR "* it87spi" " (for flash ROMs behind an ITE IT87xx Super I/O LPC/SPI \ -translation unit)" -.sp .BR "* ft2232_spi" " (for SPI flash ROMs attached to an FT2232/FT4232H family \ based USB SPI programmer)" .sp @@ -286,17 +283,17 @@ .B " flashrom \-p internal:boardmismatch=force" .sp If your mainboard uses an ITE IT87 series Super I/O for LPC<->SPI flash bus -translation, flashrom should autodetect that configuration. You can use the +translation, flashrom should autodetect that configuration. If you want to +set the I/O base port of the IT87 series SPI controller manually instead of +using the value provided by the BIOS, use the .sp .B " flashrom \-p internal:it87spiport=portnum" .sp -syntax as explained in the -.B it87spi -programmer section to use a non-default port for controlling the IT87 series -Super I/O. In the unlikely case flashrom doesn't detect an active -IT87 LPC<->SPI bridge, you can try to force recognition by using the -.B it87spi -programmer. +syntax where +.B portnum +is the I/O port number (must be a multiple of 8). In the unlikely case +flashrom doesn't detect an active IT87 LPC<->SPI bridge, please send a bug +report so we can diagnose the problem. .sp Using flashrom on laptops is dangerous and may easily make your hardware unusable (see also the @@ -320,9 +317,18 @@ dumb idea. .TP .BR "dummy " programmer +The dummy programmer operates on a buffer in memory only. It provides a safe +and fast way to test various aspects of flashrom and is mainly used in +development and while debugging. +.sp +It is able to emulate some chips to a certain degree (basic +identify/read/erase/write operations work). +.sp An optional parameter specifies the bus types it should support. For that you have to use the -.B "flashrom \-p dummy:bus=[type[+type[+type]]]" +.sp +.B " flashrom \-p dummy:bus=[type[+type[+type]]]" +.sp syntax where .B type can be @@ -332,6 +338,52 @@ .sp Example: .B "flashrom \-p dummy:bus=lpc+fwh" +.sp +The dummy programmer supports flash chip emulation for automated self-tests +without hardware access. If you want to emulate a flash chip, use the +.sp +.B " flashrom \-p dummy:emulate=chip" +.sp +syntax where +.B chip +is one of the following chips (please specify only the chip name, not the +vendor): +.sp +.RB "* ST " M25P10.RES " SPI flash chip (RES, page write)" +.sp +.RB "* SST " SST25VF040.REMS " SPI flash chip (REMS, byte write)" +.sp +.RB "* SST " SST25VF032B " SPI flash chip (RDID, AAI write)" +.sp +Example: +.B "flashrom -p dummy:emulate=SST25VF040.REMS" +.sp +If you use flash chip emulation, flash image persistence is available as well +by using the +.sp +.B " flashrom \-p dummy:emulate=chip,image=image.rom" +.sp +syntax where +.B image.rom +is the file where the simulated chip contents are read on flashrom startup and +where the chip contents on flashrom shutdown are written to. +.sp +Example: +.B "flashrom -p dummy:emulate=M25P10.RES,image=dummy.bin" +.sp +If you use SPI flash chip emulation for a chip which supports SPI page write +with the default opcode, you can set the maximum allowed write chunk size with +the +.sp +.B " flashrom \-p dummy:emulate=chip,spi_write_256_chunksize=size" +.sp +syntax where +.B size +is the number of bytes (min. 1, max. 256). +.sp +Example: +.sp +.B " flashrom -p dummy:emulate=M25P10.RES,spi_write_256_chunksize=5" .TP .BR "nic3com" , " nicrealtek" , " nicsmc1211" , " nicnatsemi" , " nicintel\ " , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii\ @@ -339,7 +391,9 @@ These programmers have an option to specify the PCI address of the card your want to use, which must be specified if more than one card supported by the selected programmer is installed in your system. The syntax is -.BR "flashrom \-p xxxx:pci=bb:dd.f" , +.sp +.BR " flashrom \-p xxxx:pci=bb:dd.f" , +.sp where .B xxxx is the name of the programmer @@ -353,19 +407,6 @@ Example: .B "flashrom \-p nic3com:pci=05:04.0" .TP -.BR "it87spi " programmer -An optional -.B it87spiport -parameter sets the I/O base port of the IT87 series SPI controller -interface to the port specified in the parameter instead of using the port -address set by the BIOS. For that you have to use the -.sp -.B " flashrom \-p it87spi:it87spiport=portnum" -.sp -syntax where -.B portnum -is an I/O port number which must be a multiple of 8. -.TP .BR "ft2232_spi " programmer An optional parameter specifies the controller type and interface/port it should support. For that you have to use the @@ -487,9 +528,6 @@ needs raw memory access, PCI configuration space access, raw I/O port access (x86) and MSR access (x86). .sp -.B it87spi -needs raw I/O port access (x86). -.sp .BR nic3com ", " nicrealtek ", " nicsmc1211 " and " nicnatsemi " need PCI configuration space read access and raw I/O port access. .sp @@ -505,6 +543,10 @@ .B satasii needs PCI configuration space read access and raw memory access. .sp +.B satamv +needs PCI configuration space read access, raw I/O port access and raw memory +access. +.sp .B serprog needs TCP access to the network or userspace access to a serial port. .sp @@ -517,8 +559,8 @@ .B dummy needs no access permissions at all. .sp -.BR internal ", " it87spi ", " nic3com ", " nicrealtek ", " nicsmc1211 ", " -.BR nicnatsemi ", " "gfxnvidia" ", " drkaiser ", " satasii " and " atahpt +.BR internal ", " nic3com ", " nicrealtek ", " nicsmc1211 ", " nicnatsemi ", " +.BR gfxnvidia ", " drkaiser ", " satasii ", " satamv " and " atahpt have to be run as superuser/root, and need additional raw access permission. .sp .BR serprog ", " buspirate_spi ", " dediprog " and " ft2232_spi

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[RFC] flashrom 0.9.4 plans
by Carl-Daniel Hailfinger 24 Jul '11

24 Jul '11

Hi, there are so many features I wanted to have in flashrom 0.9.4, but delaying the release further is not going to help anyone. Stefan Tauner probably has a few odd fixes in his queue, and I'm trying to find an acceptable fix for a segfault, and to spot the logic inversion which makes the write failure recovery code spit out the wrong message. I found a (corruption) bug in ICH IDSEL handling, need to post that fix and get it tested. Anything else we need for 0.9.4? Do we have any other unmerged bugfixes? Doc fixes? The man page is missing some features. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1382 - trunk
by repository service 24 Jul '11

24 Jul '11

Author: stefanct Date: Sun Jul 24 18:30:31 2011 New Revision: 1382 URL: http://flashrom.org/trac/flashrom/changeset/1382 Log: mark some ck804 boards as not working P5N-E SLI, EP-8NPA7I and EP-9NPA7I all need at least this patch: http://patchwork.coreboot.org/patch/2125/ the P5N-E also needs a board enable: http://patchwork.coreboot.org/patch/3298/ mark the boards as not working until those are merged. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Jul 24 17:34:56 2011 (r1381) +++ trunk/board_enable.c Sun Jul 24 18:30:31 2011 (r1382) @@ -2027,7 +2027,7 @@ {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, P3, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, P3, "Elitegroup", "K7VTA3", 256, OK, NULL}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, P3, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e}, - {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, NULL, NULL, NULL, P3, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise}, + {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "8NPA7I", NULL, NULL, P3, "EPoX", "EP-8NPA7I", 0, NT, nvidia_mcp_gpio4_raise}, /* needs http://patchwork.coreboot.org/patch/2125/ */ {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, P3, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", P3, "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise}, {0x10de, 0x02f0, 0x105b, 0x0d01, 0x10de, 0x0264, 0x105b, 0x0d01, NULL, NULL, NULL, P3, "Foxconn", "6150K8MD-8EKRSH", 0, NT, nvidia_mcp_gpio2_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sun Jul 24 17:34:56 2011 (r1381) +++ trunk/print.c Sun Jul 24 18:30:31 2011 (r1382) @@ -480,6 +480,7 @@ B("ASUS", "P5KC", 1, "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj", NULL), B("ASUS", "P5L-MX", 1, "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH", NULL), B("ASUS", "P5GD1 Pro", 1, "http://www.asus.com/product.aspx?P_ID=50M49xQh71EZOeM1", NULL), + B("ASUS", "P5N-E SLI", 0, "http://www.asus.com/product.aspx?P_ID=KyHOsOKWujC2QguJ", "Needs a patch (http://patchwork.coreboot.org/patch/2125/) and a board enable (http://patchwork.coreboot.org/patch/3298/)."), B("ASUS", "P5N32-E SLI", 1, "http://www.asus.com/product.aspx?P_ID=vBZLIBtPzYB2bLcb", NULL), B("ASUS", "P5ND2-SLI Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=WY7XroDuUImVbgp5", NULL), B("ASUS", "P5PE-VM", 1, "http://www.asus.com/product.aspx?P_ID=k3h0ZFVu9Lo1dUvk", NULL), @@ -509,7 +510,8 @@ B("Elitegroup", "RS485M-M", 1, "http://www.ecs.com.tw/ECSWebSite_2007/Products/ProductsDetail.aspx?Category…", NULL), B("Emerson", "ATCA-7360", 1, "http://www.emerson.com/sites/Network_Power/en-US/Products/Product_Detail/Pr…", NULL), B("EPoX", "EP-8K5A2", 1, "http://www.epox.com/product.asp?ID=EP-8K5A2", NULL), - B("EPoX", "EP-8NPA7I", 1, "http://epox.com/product.asp?ID=EP-8NPA7I", NULL), + B("EPoX", "EP-8NPA7I", 0, "http://www.epox.com/product.asp?ID=EP-8NPA7I", "Needs a patch (http://patchwork.coreboot.org/patch/2125/)."), + B("EPoX", "EP-9NPA7I", 0, "http://www.epox.com/product.asp?ID=EP-9NPA7I", "Needs a patch (http://patchwork.coreboot.org/patch/2125/) and the same board enable as the EP-8NPA7I."), B("EPoX", "EP-8RDA3+", 1, "http://www.epox.com/product.asp?ID=EP-8RDA3plus", NULL), B("EPoX", "EP-BX3", 1, "http://www.epox.com/product.asp?ID=EP-BX3", NULL), B("EVGA", "132-CK-NF78", 1, "http://http://www.evga.com/articles/385.asp", NULL),

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Re: [flashrom] Don't Understand Output
by Stefan Tauner 24 Jul '11

24 Jul '11

On Sat, 23 Jul 2011 12:58:19 -0400 Bryan Moore <moore.bryan(a)gmail.com> wrote: > I'm just starting to consider flashing my EeePC 1005HA's BIOS on Ubuntu > Oneiric, so I installed flashrom and ran it, but can't make heads-or-tails > of the output; I also can't find any sensible information in the FAQ or > anywhere else on the web. Help? > > flashrom output: > > > Found chipset "Intel ICH7M", enabling flash write... OK. > > This chipset supports the following protocols: FWH. > > No EEPROM/flash device found. > > Note: flashrom can never write if the flash chip isn't found automatically. hello bryan! well the message "No EEPROM/flash device found." is the most important thing there. flashrom can not detect any flash chip (which holds the bios/firmware code). there can be multiple reasons for that, but all the details do not really matter. it boils down to the fact, that laptops are harder to support in flashrom than desktop boards. you can read about a few of the details here: http://flashrom.org/Laptops we recommend to not try to update the bios of laptops, but use the vendor tools instead. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] ichspi.c: do not print PBR[3] for ICH7 because it does not exist
by Carl-Daniel Hailfinger 24 Jul '11

24 Jul '11

Am 24.07.2011 00:49 schrieb Stefan Tauner: > intel document 307013 (ICH7 datasheet) section 21.1.9 does only define > PBR[0] (at SPIBAR + 60h) to PBR[2] (SPIBAR + 68h). SPIBAR + 6Ch and following > are not defined, but we were printing them as PBR[3] anyway. i could not find > any references to PBR[3] in documentation of other related chips (NM10, > atom e6xx) either, hence kill it. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Good spotting. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1381 - trunk
by repository service 24 Jul '11

24 Jul '11

Author: stefanct Date: Sun Jul 24 17:34:56 2011 New Revision: 1381 URL: http://flashrom.org/trac/flashrom/changeset/1381 Log: ichspi.c: do not print PBR[3] for ICH7 because it does not exist intel document 307013 (ICH7 datasheet) section 21.1.9 does only define PBR[0] (at SPIBAR + 60h) to PBR[2] (SPIBAR + 68h). SPIBAR + 6Ch and following are not defined, but we were printing them as PBR[3] anyway. i could not find any references to PBR[3] in documentation of other related chips (NM10, atom e6xx) either, hence kill it. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Thu Jul 21 23:21:04 2011 (r1380) +++ trunk/ichspi.c Sun Jul 24 17:34:56 2011 (r1381) @@ -1263,7 +1263,7 @@ mmio_readl(ich_spibar + 0x58)); msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c)); - for (i = 0; i < 4; i++) { + for (i = 0; i < 3; i++) { int offs; offs = 0x60 + (i * 4); msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,

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flashrom July 2011