flashrom July 2011

flashrom@flashrom.org

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[PATCH] Random manpage improvements and updates
by Uwe Hermann 25 Jul '11

25 Jul '11

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1387 - trunk
by repository service 25 Jul '11

25 Jul '11

Author: uwe Date: Mon Jul 25 23:12:57 2011 New Revision: 1387 URL: http://flashrom.org/trac/flashrom/changeset/1387 Log: Random manpage improvements and updates. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashrom.8 Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Mon Jul 25 22:38:52 2011 (r1386) +++ trunk/flashrom.8 Mon Jul 25 23:12:57 2011 (r1387) @@ -1,4 +1,4 @@ -.TH FLASHROM 8 "Jun 14, 2011" +.TH FLASHROM 8 "Jul 25, 2011" .SH NAME flashrom \- detect, read, write, verify and erase flash chips .SH SYNOPSIS @@ -12,13 +12,14 @@ .B flashrom is a utility for detecting, reading, writing, verifying and erasing flash chips. It's often used to flash BIOS/EFI/coreboot/firmware images in-system -using a supported mainboard, but it also supports flashing of network cards -(NICs), SATA controller cards, and other external devices which can program -flash chips. +using a supported mainboard. However, it also supports various external +PCI/USB/parallel-port/serial-port based devices which can program flash chips, +including some network cards (NICs), SATA/IDE controller cards, graphics cards, +the Bus Pirate device, various FTDI FT2232/FT4232H based USB devices, and more. .PP It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, TSOP40, -and TSOP48 chips, which use various protocols such as LPC, FWH, parallel flash, -or SPI. +TSOP48, and BGA chips, which use various protocols such as LPC, FWH, +parallel flash, or SPI. .SH OPTIONS .B IMPORTANT: Please note that the command line interface for flashrom will change before @@ -30,7 +31,7 @@ or no operation. If no operation is specified, flashrom will only probe for flash chips. It is recommended that if you try flashrom the first time on a system, you run it -in probe only mode and check the output. Also you are advised to make a +in probe-only mode and check the output. Also you are advised to make a backup of your current ROM contents with .B \-r before you try to write a new image. @@ -38,6 +39,7 @@ .B "\-r, \-\-read <file>" Read flash ROM contents and save them into the given .BR <file> . +If the file already exists, it will be overwritten. .TP .B "\-w, \-\-write <file>" Write @@ -144,7 +146,8 @@ from flash layout. .TP .B "\-L, \-\-list\-supported" -List the flash chips, chipsets, mainboards, and PCI card "programmers" +List the flash chips, chipsets, mainboards, and external programmers +(including PCI, USB, parallel port, and serial port based devices) supported by flashrom. .sp There are many unlisted boards which will work out of the box, without @@ -160,8 +163,9 @@ Same as .BR \-\-list\-supported , but outputs the supported hardware in MediaWiki syntax, so that it can be -easily pasted into the wiki page at http://www.flashrom.org/. Please note -that MediaWiki output is not compiled in by default. +easily pasted into the wiki page at +.BR http://www.flashrom.org/ . +Please note that MediaWiki output is not compiled in by default. .TP .B "\-p, \-\-programmer <name>[:parameter[,parameter[,parameter]]]" Specify the programmer device. Currently supported are: @@ -489,7 +493,7 @@ four. Make sure to not forget the "0x" prefix for hexadecimal port addresses. .sp More information about the hardware is available at -http://rayer.ic.cz/elektro/spipgm.htm +.BR http://rayer.ic.cz/elektro/spipgm.htm . .TP .BR "ogp_spi " programmer The flash ROM chip to access must be specified with the @@ -517,7 +521,7 @@ section above. .sp More information about the hardware is available at -http://wiki.opengraphics.org +.BR http://wiki.opengraphics.org . .SH EXIT STATUS flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem (/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails. @@ -571,8 +575,10 @@ needs PCI configuration space read access and raw memory access. .sp On OpenBSD, you can obtain raw access permission by setting -securelevel=-1 in /etc/rc.securelevel and rebooting, or rebooting into single -user mode. +.B "securelevel=-1" +in +.B "/etc/rc.securelevel" +and rebooting, or rebooting into single user mode. .SH BUGS Please report any bugs at .sp @@ -590,6 +596,10 @@ backup. This is caused by the embedded controller (EC) present in many laptops, which interacts badly with any flash attempts. This is a hardware limitation and flashrom will attempt to detect it and abort immediately for safety reasons. +.sp +More information about flashrom on laptops is available from +.sp +.B " http://www.flashrom.org/Laptops" .SH LICENSE .B flashrom is covered by the GNU General Public License (GPL), version 2. Some files are

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Re: [flashrom] [PATCH] fix output for multiple found flash chips
by Stefan Tauner 25 Jul '11

25 Jul '11

On Fri, 24 Jun 2011 19:03:52 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > - missing quotes > - missing commas > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > cli_classic.c | 7 ++++--- > 1 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/cli_classic.c b/cli_classic.c > index 59096a0..aba6edf 100644 > --- a/cli_classic.c > +++ b/cli_classic.c > @@ -373,9 +373,10 @@ int cli_classic(int argc, char *argv[]) > } > > if (chipcount > 1) { > - printf("Multiple flash chips were detected:"); > - for (i = 0; i < chipcount; i++) > - printf(" %s", flashes[i].name); > + printf("Multiple flash chips were detected: \"%s\"", > + flashes[0].name); > + for (i = 1; i < chipcount; i++) > + printf(", \"%s\"", flashes[i].name); > printf("\nPlease specify which chip to use with the -c <chipname> option.\n"); > programmer_shutdown(); > exit(1); since no one else has reviewed this yet and it is fairly trivial, i will add it with my next "tested stuff" commit -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 6

[commit] r1386 - trunk
by repository service 25 Jul '11

25 Jul '11

Author: stefanct Date: Mon Jul 25 22:38:52 2011 New Revision: 1386 URL: http://flashrom.org/trac/flashrom/changeset/1386 Log: add a bunch of new/tested stuff and various small changes 5 - mark EN25F80 as fully tested http://www.flashrom.org/pipermail/flashrom/2011-July/007329.html - mark W25Q16 as fully tested http://www.flashrom.org/pipermail/flashrom/2011-July/007151.html - mark W39V040A as fully tested http://www.flashrom.org/pipermail/flashrom/2011-July/007161.html - mark Pm25LV040 as fully tested reported by TL1 on IRC - mark W49F002U/N as fully tested http://paste.flashrom.org/view.php?id=733g - mark W39V080FA as fully tested http://www.flashrom.org/pipermail/flashrom/2011-July/007225.html - add ASUS P4S533-X to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-July/007200.html - add ASUS M4A785TD-V EVO to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-July/007329.html - add GA-945PL-S3P (rev. 6.6) to the list of supported boards reported by TL1 on IRC - add MS-7142 (K8MM-V) to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-July/007161.html - add MS-7369 (K9N Neo V2) to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-July/007181.html - add X7DBT-INF to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-July/007225.html - mark SiS 645DX chipset enable as OK http://www.flashrom.org/pipermail/flashrom/2011-July/007200.html - mark SiS 651 chipset enable as OK http://paste.flashrom.org/view.php?id=733 - move intel_ich_gpio34_raise to the correct line(s) - change the output of unlock_w39_fwh_block from 0x%x to 0x%08x - fix output for untested chipset enables (missing space) - reorder the board enable in print.c entry for GA-8SIMLH added in r1385. - minor other fixes - fix output for multiple found flash chips by adding quotes and commas - similarly fix output of "Found/Assuming" chips Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> the last two points are Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> everything else is Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/chipset_enable.c trunk/cli_classic.c trunk/flashchips.c trunk/flashrom.c trunk/print.c trunk/w39.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Mon Jul 25 19:25:24 2011 (r1385) +++ trunk/board_enable.c Mon Jul 25 22:38:52 2011 (r1386) @@ -1475,15 +1475,6 @@ /* * Suited for: - * - ASUS A8Jm (laptop): Intel 945 + ICH7 - */ -static int intel_ich_gpio34_raise(void) -{ - return intel_ich_gpio_set(34, 1); -} - -/* - * Suited for: * - MSI MS-7046: LGA775 + 915P + ICH6 */ static int intel_ich_gpio19_raise(void) @@ -1521,6 +1512,15 @@ /* * Suited for: + * - ASUS A8Jm (laptop): Intel 945 + ICH7 + */ +static int intel_ich_gpio34_raise(void) +{ + return intel_ich_gpio_set(34, 1); +} + +/* + * Suited for: * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M */ static int intel_ich_gpio43_raise(void) @@ -2035,8 +2035,8 @@ {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise}, {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, - {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7002, 0x1458, 0x5004, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw}, {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, + {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7002, 0x1458, 0x5004, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw}, {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10de, 0x00e4, 0x1458, 0x0c11, 0x10de, 0x00e0, 0x1458, 0x0c11, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8NS Pro-939", 0, NT, nvidia_mcp_gpio0a_raise}, Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Mon Jul 25 19:25:24 2011 (r1385) +++ trunk/chipset_enable.c Mon Jul 25 22:38:52 2011 (r1386) @@ -1031,10 +1031,10 @@ {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540}, {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540}, {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540}, - {0x1039, 0x0646, NT, "SiS", "645DX", enable_flash_sis540}, + {0x1039, 0x0646, OK, "SiS", "645DX", enable_flash_sis540}, {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis540}, {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis540}, - {0x1039, 0x0651, NT, "SiS", "651", enable_flash_sis540}, + {0x1039, 0x0651, OK, "SiS", "651", enable_flash_sis540}, {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540}, {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540}, {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis540}, @@ -1229,7 +1229,7 @@ msg_pinfo("Found chipset \"%s %s\"", chipset_enables[i].vendor_name, chipset_enables[i].device_name); - msg_pdbg("with PCI ID %04x:%04x", + msg_pdbg(" with PCI ID %04x:%04x", chipset_enables[i].vendor_id, chipset_enables[i].device_id); msg_pinfo(". "); Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Mon Jul 25 19:25:24 2011 (r1385) +++ trunk/cli_classic.c Mon Jul 25 22:38:52 2011 (r1386) @@ -380,9 +380,10 @@ } if (chipcount > 1) { - printf("Multiple flash chips were detected:"); - for (i = 0; i < chipcount; i++) - printf(" %s", flashes[i].name); + printf("Multiple flash chips were detected: \"%s\"", + flashes[0].name); + for (i = 1; i < chipcount; i++) + printf(", \"%s\"", flashes[i].name); printf("\nPlease specify which chip to use with the -c <chipname> option.\n"); ret = 1; goto out_shutdown; Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Mon Jul 25 19:25:24 2011 (r1385) +++ trunk/flashchips.c Mon Jul 25 22:38:52 2011 (r1386) @@ -3075,7 +3075,7 @@ .total_size = 1024, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -5047,7 +5047,7 @@ .model_id = PMC_PM25LV040, .total_size = 512, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -7878,7 +7878,7 @@ .total_size = 2048, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -8384,9 +8384,9 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = 10, + .probe_timing = 10, .block_erasers = { { @@ -8585,7 +8585,7 @@ .total_size = 256, .page_size = 128, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10, .block_erasers = @@ -8705,7 +8705,7 @@ .total_size = 1024, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10, .block_erasers = Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Mon Jul 25 19:25:24 2011 (r1385) +++ trunk/flashrom.c Mon Jul 25 22:38:52 2011 (r1386) @@ -1201,7 +1201,7 @@ snprintf(location, sizeof(location), "on %s", programmer_table[programmer].name); tmp = flashbuses_to_text(flash->bustype); - msg_cinfo("%s chip \"%s %s\" (%d kB, %s) %s.\n", + msg_cinfo("%s %s flash chip \"%s\" (%d kB, %s) %s.\n", force ? "Assuming" : "Found", fill_flash->vendor, fill_flash->name, fill_flash->total_size, tmp, location); free(tmp); @@ -1711,7 +1711,7 @@ ret = 1; } /* It would be favorable if we could also check for correct terminaion - * of the follwing arrays, but we don't know their size in here... + * of the following arrays, but we don't know their sizes in here... * For 'flashchips' we check the first element to be non-null. In the * other cases there exist use cases where the first element can be * null. */ Modified: trunk/print.c ============================================================================== --- trunk/print.c Mon Jul 25 19:25:24 2011 (r1385) +++ trunk/print.c Mon Jul 25 22:38:52 2011 (r1386) @@ -448,6 +448,7 @@ B("ASUS", "M3A76-CM", 1, "http://www.asus.com/product.aspx?P_ID=aU8effdifLvraVze", NULL), B("ASUS", "M3A78-EM", 1, "http://www.asus.com/product.aspx?P_ID=KjpYqzmAd9vsTM2D", NULL), B("ASUS", "M4A78-EM", 1, "http://www.asus.com/product.aspx?P_ID=0KyowHKUFAQqH2DO", NULL), + B("ASUS", "M4A785TD-V EVO", 1, "http://www.asus.com/product.aspx?P_ID=fcsXWSxnhzZE9rnR", NULL), B("ASUS", "M4A785TD-M EVO", 1, "http://www.asus.com/product.aspx?P_ID=QHbvGVB1mXmmD8qQ", NULL), B("ASUS", "M4A79T Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=lhJiLTN5huPfCVkW", NULL), B("ASUS", "M4A87TD/USB3", 1, "http://www.asus.com/product.aspx?P_ID=nlWYrI9wlNIYHAaa", NULL), @@ -470,13 +471,14 @@ B("ASUS", "P4P800-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=INIJUvLlif7LHp3g", NULL), B("ASUS", "P4SC-E", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock478/p4sc-e/", "Part of ASUS Terminator P4 533 barebone system"), B("ASUS", "P4SD-LA", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00022505", NULL), + B("ASUS", "P4S533-X", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock478/p4s533-x/", NULL), B("ASUS", "P4S800-MX", 1, "http://www.asus.com/product.aspx?P_ID=Bb57zoJhmO1Qkcrh", NULL), B("ASUS", "P5A", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock7/ali/p5a/", NULL), B("ASUS", "P5B", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B/", NULL), B("ASUS", "P5B-Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=bswT66IBSb2rEWNa", NULL), B("ASUS", "P5BV-M", 0, "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B-VM/", "Reported by Bernhard M. Wiedemann <bernhard(a)uml12d.zq1.de> to flashrom(a)coreboot.org, no public archive. Missing board enable and/or SST49LF008A unlocking. May work now."), B("ASUS", "P5GC-MX/1333", 1, "http://www.asus.com/product.aspx?P_ID=PYvbfOokwxUzJky3", NULL), - B("ASUS", "P5GDC Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=AbeoopyNpI2TZixg", NULL), + B("ASUS", "P5GDC Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=AbeoopyNpI2TZixg", NULL), B("ASUS", "P5KC", 1, "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj", NULL), B("ASUS", "P5L-MX", 1, "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH", NULL), B("ASUS", "P5GD1 Pro", 1, "http://www.asus.com/product.aspx?P_ID=50M49xQh71EZOeM1", NULL), @@ -534,8 +536,9 @@ B("GIGABYTE", "GA-7ZM", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1366", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option."), B("GIGABYTE", "GA-8IP775", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1830", NULL), B("GIGABYTE", "GA-8IRML", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1343", NULL), - B("GIGABYTE", "GA-8SIMLH", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1399", NULL), B("GIGABYTE", "GA-8PE667 Ultra 2", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1607", NULL), + B("GIGABYTE", "GA-8SIMLH", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1399", NULL), + B("GIGABYTE", "GA-945PL-S3P (rev. 6.6)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2541", NULL), B("GIGABYTE", "GA-965GM-S2 (rev. 2.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2617", NULL), B("GIGABYTE", "GA-965P-DS4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2288", NULL), B("GIGABYTE", "GA-EP35-DS3L", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), @@ -602,6 +605,7 @@ B("MSI", "MS-7061 (KM3M-V/KM4M-V/KM4AM-V)", 1, "http://www.msi.com/service/search/?kw=7061&type=product", NULL), B("MSI", "MS-7065", 1, "http://browse.geekbench.ca/geekbench2/view/53114", NULL), B("MSI", "MS-7135 (K8N Neo3)", 1, "http://www.msi.com/product/mb/K8N-Neo3.html", NULL), + B("MSI", "MS-7142 (K8MM-V)", 1, "http://www.msi.com/product/mb/K8MM-V.html", NULL), B("MSI", "MS-7168 (Orion)", 1, "http://support.packardbell.co.uk/uk/item/index.php?i=spec_orion&pi=platform…", NULL), B("MSI", "MS-7207 (K8NGM2-L)", 1, "http://www.msi.com/product/mb/K8NGM2-FID--IL--L.html", NULL), B("MSI", "MS-7211 (PM8M3-V)", 1, "http://www.msi.com/product/mb/PM8M3-V.html", NULL), @@ -612,6 +616,7 @@ B("MSI", "MS-7312 (K9MM-V)", 1, "http://www.msi.com/product/mb/K9MM-V.html", NULL), B("MSI", "MS-7345 (P35 Neo2-FIR)", 1, "http://www.msi.com/product/mb/P35-Neo2-FR---FIR.html", NULL), B("MSI", "MS-7368 (K9AG Neo2-Digital)", 1, "http://www.msi.com/product/mb/K9AG-Neo2-Digital.html", NULL), + B("MSI", "MS-7369 (K9N Neo V2)", 1, "http://www.msi.com/product/mb/K9N-Neo-V2.html", NULL), B("MSI", "MS-7376 (K9A2 Platinum V1)", 1, "http://www.msi.com/product/mb/K9A2-Platinum.html", NULL), B("MSI", "MS-7529 (G31M3-L(S) V2)", 1, "http://www.msi.com/product/mb/G31M3-L-V2---G31M3-LS-V2.html", NULL), B("MSI", "MS-7529 (G31TM-P21)", 1, "http://www.msi.com/product/mb/G31TM-P21.html", NULL), @@ -648,6 +653,7 @@ B("Sun", "Fire x4600", 0, "http://www.sun.com/servers/x64/x4600/", "No public report found. May work now."), B("Supermicro", "H8QC8", 1, "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm", NULL), B("Supermicro", "X5DP8-G2", 1, "http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DP8-G2.cfm", NULL), + B("Supermicro", "X7DBT-INF", 1, "http://www.supermicro.com/products/motherboard/Xeon1333/5000P/X7DBT-INF.cfm", NULL), B("Supermicro", "X7SPA-HF", 1, "http://www.supermicro.com/products/motherboard/ATOM/ICH9/X7SPA.cfm?typ=H&IP…", NULL), B("Supermicro", "X8DT3", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DT3.cfm", NULL), B("Supermicro", "X8DTH-6F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTH-6F.cfm", NULL), Modified: trunk/w39.c ============================================================================== --- trunk/w39.c Mon Jul 25 19:25:24 2011 (r1385) +++ trunk/w39.c Mon Jul 25 22:38:52 2011 (r1386) @@ -70,10 +70,10 @@ if (locking & ((1 << 2) | (1 << 0))) { /* Lockdown active? */ if (locking & (1 << 1)) { - msg_cerr("Can't unlock block at 0x%x!\n", offset); + msg_cerr("Can't unlock block at 0x%08x!\n", offset); return -1; } else { - msg_cdbg("Unlocking block at 0x%x\n", offset); + msg_cdbg("Unlocking block at 0x%08x\n", offset); chip_writeb(0, wrprotect); } }

1 0

No luck with a Marvell 88SX7042 (Adaptec 1430SA)
by Tim Small 25 Jul '11

25 Jul '11

Hi, The Adaptec 1430SA is a Marvell 88SX7042 based controller. It has a different vendor/device ID pair when using the Adaptec firmware, so I added this in: --- satamv.c (revision 1364) +++ satamv.c (working copy) @@ -30,6 +30,7 @@ const struct pcidev_status satas_mv[] = { /* 88SX6041 and 88SX6042 are the same according to the datasheet. */ {0x11ab, 0x7042, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II"}, + {0x9005, 0x0243, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II (Adaptec 1430SA)"}, {}, }; ... but it doesn't seem to work on the Adaptec card: flashrom -p satamv:pci=06:00.0 flashrom v0.9.3-r1364 on Linux 2.6.39-2-amd64 (x86_64), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found "Marvell 88SX7042 PCI-e 4-port SATA-II (Adaptec 1430SA)" (9005:0243, BDF 06:00.0). Warning! Either the straps are incorrect or you have no flash or someone overwrote the strap values! No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. The eeprom on the card is an AMD Am29LV004BT (which is supported for probing). Cheers, Tim. -- South East Open Source Solutions Limited Registered in England and Wales with company number 06134732. Registered Office: 2 Powell Gardens, Redhill, Surrey, RH1 1TQ VAT number: 900 6633 53 http://seoss.co.uk/ +44-(0)1273-808309

2 3

Re: [flashrom] [PATCH] Add support for the GIGABYTE GA-8SIMLH board.
by Stefan Tauner 25 Jul '11

25 Jul '11

On Sun, 24 Jul 2011 20:47:12 +0200 Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> wrote: > The usage of the GPIO output register as bitmap can be confirmed from the > vendor board enable code, so the comment has been deleted. It really is > (1<<gpionumber). > > lspci: http://paste.flashrom.org/view.php?id=729 > superiotool: http://paste.flashrom.org/view.php?id=730 > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> since it has apparently worked (http://paste.flashrom.org/view.php?id=733) and looks fine otherwise, this is Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> two minor nitpicks: > + {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7012, 0x1458, 0xa002, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw}, the second device is the sound card, which could presumably be disabled. there is only one other device with a gigabyte vendor id: 1458:5004 (usb2.0 controller). not sure if that would be better, just wanted to mention it. > B("GIGABYTE", "GA-8IRML", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1343", NULL), > + B("GIGABYTE", "GA-8SIMLH", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1399", NULL), > B("GIGABYTE", "GA-8PE667 Ultra 2", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1607", NULL), P < S, so the new one should be below the GA-8PE667. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 2

[commit] r1385 - trunk
by repository service 25 Jul '11

25 Jul '11

Author: mkarcher Date: Mon Jul 25 19:25:24 2011 New Revision: 1385 URL: http://flashrom.org/trac/flashrom/changeset/1385 Log: Add support for the GIGABYTE GA-8SIMLH board. The usage of the GPIO output register as bitmap can be confirmed from the vendor board enable code, so the comment has been deleted. It really is (1<<gpionumber). flashrom -V: http://paste.flashrom.org/view.php?id=728 lspci: http://paste.flashrom.org/view.php?id=729 superiotool: http://paste.flashrom.org/view.php?id=730 test report: http://paste.flashrom.org/view.php?id=733 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Mon Jul 25 00:21:57 2011 (r1384) +++ trunk/board_enable.c Mon Jul 25 19:25:24 2011 (r1385) @@ -1725,12 +1725,13 @@ } /* - * Enable some GPIO pin on SiS southbridge. + * Enable some GPIO pin on SiS southbridge and enables SIO flash writes. * * Suited for: * - MSI 651M-L: SiS651 / SiS962 + * - GIGABYTE GA-8SIMLH */ -static int board_msi_651ml(void) +static int sis_gpio0_raise_and_w836xx_memw(void) { struct pci_dev *dev; uint16_t base, temp; @@ -1741,7 +1742,6 @@ return 1; } - /* Registers 68 and 64 seem like bitmaps. */ base = pci_read_word(dev, 0x74); temp = INW(base + 0x68); temp &= ~(1 << 0); /* Make pin output? */ @@ -2035,6 +2035,7 @@ {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise}, {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, + {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7002, 0x1458, 0x5004, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw}, {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, @@ -2063,7 +2064,7 @@ {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise}, - {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, + {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, sis_gpio0_raise_and_w836xx_memw}, {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Mon Jul 25 00:21:57 2011 (r1384) +++ trunk/print.c Mon Jul 25 19:25:24 2011 (r1385) @@ -534,6 +534,7 @@ B("GIGABYTE", "GA-7ZM", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1366", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option."), B("GIGABYTE", "GA-8IP775", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1830", NULL), B("GIGABYTE", "GA-8IRML", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1343", NULL), + B("GIGABYTE", "GA-8SIMLH", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1399", NULL), B("GIGABYTE", "GA-8PE667 Ultra 2", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1607", NULL), B("GIGABYTE", "GA-965GM-S2 (rev. 2.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2617", NULL), B("GIGABYTE", "GA-965P-DS4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2288", NULL),

1 0

Re: [flashrom] [Patch] Add support for EN25Q series SPI flash chips
by Stefan Tauner 24 Jul '11

24 Jul '11

On Wed, 22 Jun 2011 16:04:42 -0700 David Hendricks <dhendrix(a)google.com> wrote: > Thanks for the review! I've attached an updated patch to address your > comments. > > I'm still not sure what the best course of action is for dealing with the > D16 versus Q16 evil twin scenario. Let's see if Carl-Daniel has further > comments. > > New patch is: > Signed-off-by: David Hendricks <dhendrix(a)google.com> since carl-daniel wants to push 0.9.4 soon (no, really! ;) i have committed your patch with some small changes which i think make it better (including the D16 -> Q16 rename) in r1384. thank you! -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[commit] r1384 - trunk
by repository service 24 Jul '11

24 Jul '11

Author: stefanct Date: Mon Jul 25 00:21:57 2011 New Revision: 1384 URL: http://flashrom.org/trac/flashrom/changeset/1384 Log: add support for EN25Q(H) series SPI flash chips - EN25Q40 - EN25Q80 - EN25Q16 (half-evil twin of already supported EN25D16, hence merged) - EN25Q32(A/B) - EN25Q64 - EN25Q128 - EN25QH16 Signed-off-by: David Hendricks <dhendrix(a)google.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sun Jul 24 20:41:13 2011 (r1383) +++ trunk/flashchips.c Mon Jul 25 00:21:57 2011 (r1384) @@ -2923,42 +2923,6 @@ { .vendor = "Eon", - .name = "EN25D16", - .bustype = CHIP_BUSTYPE_SPI, - .manufacture_id = EON_ID_NOPREFIX, - .model_id = EON_EN25D16, - .total_size = 2048, - .page_size = 256, - .tested = TEST_UNTESTED, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {4 * 1024, 512} }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {64 * 1024, 32} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {64 * 1024, 32} }, - .block_erase = spi_block_erase_52, - }, { - .eraseblocks = { {2 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_60, - }, { - .eraseblocks = { {2 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, - }, - - { - .vendor = "Eon", .name = "EN25F05", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = EON_ID_NOPREFIX, @@ -3205,6 +3169,259 @@ }, { + .vendor = "Eon", + .name = "EN25Q40", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25Q40, + .total_size = 512, + .page_size = 256, + /* TODO: chip features 256-byte one-time programmable region */ + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN25Q80(A)", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25Q80, + .total_size = 1024, + .page_size = 256, + /* TODO: chip features 256-byte one-time programmable region */ + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + /* Note: EN25D16 is an evil twin which shares the model ID + but has different write protection capabilities */ + .vendor = "Eon", + .name = "EN25Q16", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25Q16, + .total_size = 2048, + .page_size = 256, + /* TODO: EN25D16 features 512-byte one-time programmable region, + * EN25Q16 features a 128-byte one-time programmable region */ + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + /* not supported by Q16 version */ + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN25Q32(A/B)", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25Q32, + .total_size = 4096, + .page_size = 256, + /* TODO: chip features 512-byte one-time programmable region */ + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN25Q64", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25Q64, + .total_size = 8192, + .page_size = 256, + /* TODO: chip features 512-byte one-time programmable region */ + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN25Q128", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25Q128, + .total_size = 16384, + .page_size = 256, + /* TODO: chip features 512-byte one-time programmable region */ + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Eon", + .name = "EN25QH16", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25QH16, + .total_size = 2048, + .page_size = 256, + /* TODO: chip features 512-byte one-time programmable region + * and supports SFDP. + */ + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 2048, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 2048, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { .vendor = "Eon", .name = "EN29F010", .bustype = CHIP_BUSTYPE_PARALLEL, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sun Jul 24 20:41:13 2011 (r1383) +++ trunk/flashchips.h Mon Jul 25 00:21:57 2011 (r1384) @@ -232,7 +232,6 @@ #define EON_EN25B64 0x2017 /* Same as P64 */ #define EON_EN25B64T 0x46 #define EON_EN25B64B 0x36 -#define EON_EN25D16 0x3015 #define EON_EN25F05 0x3110 #define EON_EN25F10 0x3111 #define EON_EN25F20 0x3112 @@ -240,6 +239,13 @@ #define EON_EN25F80 0x3114 #define EON_EN25F16 0x3115 #define EON_EN25F32 0x3116 +#define EON_EN25Q40 0x3013 +#define EON_EN25Q80 0x3014 +#define EON_EN25Q16 0x3015 /* Same as EN25D16 */ +#define EON_EN25Q32 0x3016 /* Same as EN25Q32A and EN25Q32B */ +#define EON_EN25Q64 0x3017 +#define EON_EN25Q128 0x3018 +#define EON_EN25QH16 0x7015 #define EON_EN29F512 0x7F21 #define EON_EN29F010 0x20 #define EON_EN29F040A 0x7F04

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Asus_EEE_PC_1201N_flashrom_v0.9.3-r1383
by Filatov Sergey Dmitrievich 24 Jul '11

24 Jul '11

-- Regards, Sergey Filatov

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flashrom July 2011