flashrom May 2011

flashrom@flashrom.org

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236 discussions

[PATCH 2/3] Shuffle code around (no other changes)
by Michael Karcher 04 May '11

04 May '11

This is to prepare the SPI registration patch without needing to do forward declarations. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- bitbang_spi.c | 84 +++++++++--------- buspirate_spi.c | 182 +++++++++++++++++++------------------- dummyflasher.c | 264 +++++++++++++++++++++++++++--------------------------- ft2232_spi.c | 170 ++++++++++++++++++------------------ it85spi.c | 103 +++++++++++----------- it87spi.c | 242 +++++++++++++++++++++++++------------------------- wbsio_spi.c | 94 ++++++++++---------- 7 files changed, 569 insertions(+), 570 deletions(-) diff --git a/bitbang_spi.c b/bitbang_spi.c index d63c769..be30944 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -64,6 +64,48 @@ static void bitbang_spi_release_bus(void) bitbang_spi_master->release_bus(); } +static uint8_t bitbang_spi_readwrite_byte(uint8_t val) +{ + uint8_t ret = 0; + int i; + + for (i = 7; i >= 0; i--) { + bitbang_spi_set_mosi((val >> i) & 1); + programmer_delay(bitbang_spi_half_period); + bitbang_spi_set_sck(1); + ret <<= 1; + ret |= bitbang_spi_get_miso(); + programmer_delay(bitbang_spi_half_period); + bitbang_spi_set_sck(0); + } + return ret; +} + +int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + int i; + + /* FIXME: Run bitbang_spi_request_bus here or in programmer init? + * Requesting and releasing the SPI bus is handled in here to allow the + * programmer to use its own SPI engine for native accesses. + */ + bitbang_spi_request_bus(); + bitbang_spi_set_cs(0); + for (i = 0; i < writecnt; i++) + bitbang_spi_readwrite_byte(writearr[i]); + for (i = 0; i < readcnt; i++) + readarr[i] = bitbang_spi_readwrite_byte(0); + + programmer_delay(bitbang_spi_half_period); + bitbang_spi_set_cs(1); + programmer_delay(bitbang_spi_half_period); + /* FIXME: Run bitbang_spi_release_bus here or in programmer init? */ + bitbang_spi_release_bus(); + + return 0; +} + int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod) { /* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type, @@ -109,45 +151,3 @@ int bitbang_spi_shutdown(const struct bitbang_spi_master *master) bitbang_spi_master = NULL; return 0; } - -static uint8_t bitbang_spi_readwrite_byte(uint8_t val) -{ - uint8_t ret = 0; - int i; - - for (i = 7; i >= 0; i--) { - bitbang_spi_set_mosi((val >> i) & 1); - programmer_delay(bitbang_spi_half_period); - bitbang_spi_set_sck(1); - ret <<= 1; - ret |= bitbang_spi_get_miso(); - programmer_delay(bitbang_spi_half_period); - bitbang_spi_set_sck(0); - } - return ret; -} - -int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr) -{ - int i; - - /* FIXME: Run bitbang_spi_request_bus here or in programmer init? - * Requesting and releasing the SPI bus is handled in here to allow the - * programmer to use its own SPI engine for native accesses. - */ - bitbang_spi_request_bus(); - bitbang_spi_set_cs(0); - for (i = 0; i < writecnt; i++) - bitbang_spi_readwrite_byte(writearr[i]); - for (i = 0; i < readcnt; i++) - readarr[i] = bitbang_spi_readwrite_byte(0); - - programmer_delay(bitbang_spi_half_period); - bitbang_spi_set_cs(1); - programmer_delay(bitbang_spi_half_period); - /* FIXME: Run bitbang_spi_release_bus here or in programmer init? */ - bitbang_spi_release_bus(); - - return 0; -} diff --git a/buspirate_spi.c b/buspirate_spi.c index e7a7a10..89f529d 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -81,6 +81,97 @@ static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigne return 0; } +int buspirate_spi_shutdown(void) +{ + unsigned char buf[5]; + int ret = 0; + + /* Exit raw SPI mode (enter raw bitbang mode) */ + buf[0] = 0x00; + ret = buspirate_sendrecv(buf, 1, 5); + if (ret) + return ret; + if (memcmp(buf, "BBIO", 4)) { + msg_perr("Entering raw bitbang mode failed!\n"); + return 1; + } + msg_pdbg("Raw bitbang mode version %c\n", buf[4]); + if (buf[4] != '1') { + msg_perr("Can't handle raw bitbang mode version %c!\n", + buf[4]); + return 1; + } + /* Reset Bus Pirate (return to user terminal) */ + buf[0] = 0x0f; + ret = buspirate_sendrecv(buf, 1, 0); + if (ret) + return ret; + + /* Shut down serial port communication */ + ret = serialport_shutdown(); + if (ret) + return ret; + msg_pdbg("Bus Pirate shutdown completed.\n"); + + return 0; +} + +int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + static unsigned char *buf = NULL; + int i = 0, ret = 0; + + if (writecnt > 16 || readcnt > 16 || (readcnt + writecnt) > 16) + return SPI_INVALID_LENGTH; + + /* 3 bytes extra for CS#, len, CS#. */ + buf = realloc(buf, writecnt + readcnt + 3); + if (!buf) { + msg_perr("Out of memory!\n"); + exit(1); // -1 + } + + /* Assert CS# */ + buf[i++] = 0x02; + + buf[i++] = 0x10 | (writecnt + readcnt - 1); + memcpy(buf + i, writearr, writecnt); + i += writecnt; + memset(buf + i, 0, readcnt); + + i += readcnt; + /* De-assert CS# */ + buf[i++] = 0x03; + + ret = buspirate_sendrecv(buf, i, i); + + if (ret) { + msg_perr("Bus Pirate communication error!\n"); + return SPI_GENERIC_ERROR; + } + + if (buf[0] != 0x01) { + msg_perr("Protocol error while lowering CS#!\n"); + return SPI_GENERIC_ERROR; + } + + if (buf[1] != 0x01) { + msg_perr("Protocol error while reading/writing SPI!\n"); + return SPI_GENERIC_ERROR; + } + + if (buf[i - 1] != 0x01) { + msg_perr("Protocol error while raising CS#!\n"); + return SPI_GENERIC_ERROR; + } + + /* Skip CS#, length, writearr. */ + memcpy(readarr, buf + 2 + writecnt, readcnt); + + return ret; +} + static const struct buspirate_spispeeds spispeeds[] = { {"30k", 0x0}, {"125k", 0x1}, @@ -235,94 +326,3 @@ int buspirate_spi_init(void) return 0; } - -int buspirate_spi_shutdown(void) -{ - unsigned char buf[5]; - int ret = 0; - - /* Exit raw SPI mode (enter raw bitbang mode) */ - buf[0] = 0x00; - ret = buspirate_sendrecv(buf, 1, 5); - if (ret) - return ret; - if (memcmp(buf, "BBIO", 4)) { - msg_perr("Entering raw bitbang mode failed!\n"); - return 1; - } - msg_pdbg("Raw bitbang mode version %c\n", buf[4]); - if (buf[4] != '1') { - msg_perr("Can't handle raw bitbang mode version %c!\n", - buf[4]); - return 1; - } - /* Reset Bus Pirate (return to user terminal) */ - buf[0] = 0x0f; - ret = buspirate_sendrecv(buf, 1, 0); - if (ret) - return ret; - - /* Shut down serial port communication */ - ret = serialport_shutdown(); - if (ret) - return ret; - msg_pdbg("Bus Pirate shutdown completed.\n"); - - return 0; -} - -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr) -{ - static unsigned char *buf = NULL; - int i = 0, ret = 0; - - if (writecnt > 16 || readcnt > 16 || (readcnt + writecnt) > 16) - return SPI_INVALID_LENGTH; - - /* 3 bytes extra for CS#, len, CS#. */ - buf = realloc(buf, writecnt + readcnt + 3); - if (!buf) { - msg_perr("Out of memory!\n"); - exit(1); // -1 - } - - /* Assert CS# */ - buf[i++] = 0x02; - - buf[i++] = 0x10 | (writecnt + readcnt - 1); - memcpy(buf + i, writearr, writecnt); - i += writecnt; - memset(buf + i, 0, readcnt); - - i += readcnt; - /* De-assert CS# */ - buf[i++] = 0x03; - - ret = buspirate_sendrecv(buf, i, i); - - if (ret) { - msg_perr("Bus Pirate communication error!\n"); - return SPI_GENERIC_ERROR; - } - - if (buf[0] != 0x01) { - msg_perr("Protocol error while lowering CS#!\n"); - return SPI_GENERIC_ERROR; - } - - if (buf[1] != 0x01) { - msg_perr("Protocol error while reading/writing SPI!\n"); - return SPI_GENERIC_ERROR; - } - - if (buf[i - 1] != 0x01) { - msg_perr("Protocol error while raising CS#!\n"); - return SPI_GENERIC_ERROR; - } - - /* Skip CS#, length, writearr. */ - memcpy(readarr, buf + 2 + writecnt, readcnt); - - return ret; -} diff --git a/dummyflasher.c b/dummyflasher.c index b6e67db..c4c9c4e 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -60,138 +60,6 @@ static int emu_jedec_ce_c7_size = 0; static int spi_write_256_chunksize = 256; -int dummy_init(void) -{ - char *bustext = NULL; - char *tmp = NULL; -#if EMULATE_CHIP - struct stat image_stat; -#endif - - msg_pspew("%s\n", __func__); - - bustext = extract_programmer_param("bus"); - msg_pdbg("Requested buses are: %s\n", bustext ? bustext : "default"); - if (!bustext) - bustext = strdup("parallel+lpc+fwh+spi"); - /* Convert the parameters to lowercase. */ - tolower_string(bustext); - - buses_supported = CHIP_BUSTYPE_NONE; - if (strstr(bustext, "parallel")) { - buses_supported |= CHIP_BUSTYPE_PARALLEL; - msg_pdbg("Enabling support for %s flash.\n", "parallel"); - } - if (strstr(bustext, "lpc")) { - buses_supported |= CHIP_BUSTYPE_LPC; - msg_pdbg("Enabling support for %s flash.\n", "LPC"); - } - if (strstr(bustext, "fwh")) { - buses_supported |= CHIP_BUSTYPE_FWH; - msg_pdbg("Enabling support for %s flash.\n", "FWH"); - } - if (strstr(bustext, "spi")) { - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_DUMMY; - msg_pdbg("Enabling support for %s flash.\n", "SPI"); - } - if (buses_supported == CHIP_BUSTYPE_NONE) - msg_pdbg("Support for all flash bus types disabled.\n"); - free(bustext); - - tmp = extract_programmer_param("spi_write_256_chunksize"); - if (tmp) { - spi_write_256_chunksize = atoi(tmp); - free(tmp); - if (spi_write_256_chunksize < 1) { - msg_perr("invalid spi_write_256_chunksize\n"); - return 1; - } - } - -#if EMULATE_CHIP - tmp = extract_programmer_param("emulate"); - if (!tmp) { - msg_pdbg("Not emulating any flash chip.\n"); - /* Nothing else to do. */ - return 0; - } -#if EMULATE_SPI_CHIP - if (!strcmp(tmp, "M25P10.RES")) { - emu_chip = EMULATE_ST_M25P10_RES; - emu_chip_size = 128 * 1024; - emu_max_byteprogram_size = 128; - emu_max_aai_size = 0; - emu_jedec_se_size = 0; - emu_jedec_be_52_size = 0; - emu_jedec_be_d8_size = 32 * 1024; - emu_jedec_ce_60_size = 0; - emu_jedec_ce_c7_size = emu_chip_size; - msg_pdbg("Emulating ST M25P10.RES SPI flash chip (RES, page " - "write)\n"); - } - if (!strcmp(tmp, "SST25VF040.REMS")) { - emu_chip = EMULATE_SST_SST25VF040_REMS; - emu_chip_size = 512 * 1024; - emu_max_byteprogram_size = 1; - emu_max_aai_size = 0; - emu_jedec_se_size = 4 * 1024; - emu_jedec_be_52_size = 32 * 1024; - emu_jedec_be_d8_size = 0; - emu_jedec_ce_60_size = emu_chip_size; - emu_jedec_ce_c7_size = 0; - msg_pdbg("Emulating SST SST25VF040.REMS SPI flash chip (REMS, " - "byte write)\n"); - } - if (!strcmp(tmp, "SST25VF032B")) { - emu_chip = EMULATE_SST_SST25VF032B; - emu_chip_size = 4 * 1024 * 1024; - emu_max_byteprogram_size = 1; - emu_max_aai_size = 2; - emu_jedec_se_size = 4 * 1024; - emu_jedec_be_52_size = 32 * 1024; - emu_jedec_be_d8_size = 64 * 1024; - emu_jedec_ce_60_size = emu_chip_size; - emu_jedec_ce_c7_size = emu_chip_size; - msg_pdbg("Emulating SST SST25VF032B SPI flash chip (RDID, AAI " - "write)\n"); - } -#endif - if (emu_chip == EMULATE_NONE) { - msg_perr("Invalid chip specified for emulation: %s\n", tmp); - free(tmp); - return 1; - } - free(tmp); - flashchip_contents = malloc(emu_chip_size); - if (!flashchip_contents) { - msg_perr("Out of memory!\n"); - return 1; - } - msg_pdbg("Filling fake flash chip with 0xff, size %i\n", emu_chip_size); - memset(flashchip_contents, 0xff, emu_chip_size); - - emu_persistent_image = extract_programmer_param("image"); - if (!emu_persistent_image) { - /* Nothing else to do. */ - return 0; - } - if (!stat(emu_persistent_image, &image_stat)) { - msg_pdbg("Found persistent image %s, size %li ", - emu_persistent_image, (long)image_stat.st_size); - if (image_stat.st_size == emu_chip_size) { - msg_pdbg("matches.\n"); - msg_pdbg("Reading %s\n", emu_persistent_image); - read_buf_from_file(flashchip_contents, emu_chip_size, - emu_persistent_image); - } else { - msg_pdbg("doesn't match.\n"); - } - } -#endif - return 0; -} - int dummy_shutdown(void) { msg_pspew("%s\n", __func__); @@ -512,3 +380,135 @@ int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int le return spi_write_chunked(flash, buf, start, len, spi_write_256_chunksize); } + +int dummy_init(void) +{ + char *bustext = NULL; + char *tmp = NULL; +#if EMULATE_CHIP + struct stat image_stat; +#endif + + msg_pspew("%s\n", __func__); + + bustext = extract_programmer_param("bus"); + msg_pdbg("Requested buses are: %s\n", bustext ? bustext : "default"); + if (!bustext) + bustext = strdup("parallel+lpc+fwh+spi"); + /* Convert the parameters to lowercase. */ + tolower_string(bustext); + + buses_supported = CHIP_BUSTYPE_NONE; + if (strstr(bustext, "parallel")) { + buses_supported |= CHIP_BUSTYPE_PARALLEL; + msg_pdbg("Enabling support for %s flash.\n", "parallel"); + } + if (strstr(bustext, "lpc")) { + buses_supported |= CHIP_BUSTYPE_LPC; + msg_pdbg("Enabling support for %s flash.\n", "LPC"); + } + if (strstr(bustext, "fwh")) { + buses_supported |= CHIP_BUSTYPE_FWH; + msg_pdbg("Enabling support for %s flash.\n", "FWH"); + } + if (strstr(bustext, "spi")) { + buses_supported |= CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_DUMMY; + msg_pdbg("Enabling support for %s flash.\n", "SPI"); + } + if (buses_supported == CHIP_BUSTYPE_NONE) + msg_pdbg("Support for all flash bus types disabled.\n"); + free(bustext); + + tmp = extract_programmer_param("spi_write_256_chunksize"); + if (tmp) { + spi_write_256_chunksize = atoi(tmp); + free(tmp); + if (spi_write_256_chunksize < 1) { + msg_perr("invalid spi_write_256_chunksize\n"); + return 1; + } + } + +#if EMULATE_CHIP + tmp = extract_programmer_param("emulate"); + if (!tmp) { + msg_pdbg("Not emulating any flash chip.\n"); + /* Nothing else to do. */ + return 0; + } +#if EMULATE_SPI_CHIP + if (!strcmp(tmp, "M25P10.RES")) { + emu_chip = EMULATE_ST_M25P10_RES; + emu_chip_size = 128 * 1024; + emu_max_byteprogram_size = 128; + emu_max_aai_size = 0; + emu_jedec_se_size = 0; + emu_jedec_be_52_size = 0; + emu_jedec_be_d8_size = 32 * 1024; + emu_jedec_ce_60_size = 0; + emu_jedec_ce_c7_size = emu_chip_size; + msg_pdbg("Emulating ST M25P10.RES SPI flash chip (RES, page " + "write)\n"); + } + if (!strcmp(tmp, "SST25VF040.REMS")) { + emu_chip = EMULATE_SST_SST25VF040_REMS; + emu_chip_size = 512 * 1024; + emu_max_byteprogram_size = 1; + emu_max_aai_size = 0; + emu_jedec_se_size = 4 * 1024; + emu_jedec_be_52_size = 32 * 1024; + emu_jedec_be_d8_size = 0; + emu_jedec_ce_60_size = emu_chip_size; + emu_jedec_ce_c7_size = 0; + msg_pdbg("Emulating SST SST25VF040.REMS SPI flash chip (REMS, " + "byte write)\n"); + } + if (!strcmp(tmp, "SST25VF032B")) { + emu_chip = EMULATE_SST_SST25VF032B; + emu_chip_size = 4 * 1024 * 1024; + emu_max_byteprogram_size = 1; + emu_max_aai_size = 2; + emu_jedec_se_size = 4 * 1024; + emu_jedec_be_52_size = 32 * 1024; + emu_jedec_be_d8_size = 64 * 1024; + emu_jedec_ce_60_size = emu_chip_size; + emu_jedec_ce_c7_size = emu_chip_size; + msg_pdbg("Emulating SST SST25VF032B SPI flash chip (RDID, AAI " + "write)\n"); + } +#endif + if (emu_chip == EMULATE_NONE) { + msg_perr("Invalid chip specified for emulation: %s\n", tmp); + free(tmp); + return 1; + } + free(tmp); + flashchip_contents = malloc(emu_chip_size); + if (!flashchip_contents) { + msg_perr("Out of memory!\n"); + return 1; + } + msg_pdbg("Filling fake flash chip with 0xff, size %i\n", emu_chip_size); + memset(flashchip_contents, 0xff, emu_chip_size); + + emu_persistent_image = extract_programmer_param("image"); + if (!emu_persistent_image) { + /* Nothing else to do. */ + return 0; + } + if (!stat(emu_persistent_image, &image_stat)) { + msg_pdbg("Found persistent image %s, size %li ", + emu_persistent_image, (long)image_stat.st_size); + if (image_stat.st_size == emu_chip_size) { + msg_pdbg("matches.\n"); + msg_pdbg("Reading %s\n", emu_persistent_image); + read_buf_from_file(flashchip_contents, emu_chip_size, + emu_persistent_image); + } else { + msg_pdbg("doesn't match.\n"); + } + } +#endif + return 0; +} diff --git a/ft2232_spi.c b/ft2232_spi.c index 7ff1d81..4e0fc67 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -128,6 +128,91 @@ static int get_buf(struct ftdi_context *ftdic, const unsigned char *buf, return 0; } +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + struct ftdi_context *ftdic = &ftdic_context; + static unsigned char *buf = NULL; + /* failed is special. We use bitwise ops, but it is essentially bool. */ + int i = 0, ret = 0, failed = 0; + int bufsize; + static int oldbufsize = 0; + + if (writecnt > 65536 || readcnt > 65536) + return SPI_INVALID_LENGTH; + + /* buf is not used for the response from the chip. */ + bufsize = max(writecnt + 9, 260 + 9); + /* Never shrink. realloc() calls are expensive. */ + if (bufsize > oldbufsize) { + buf = realloc(buf, bufsize); + if (!buf) { + msg_perr("Out of memory!\n"); + exit(1); + } + oldbufsize = bufsize; + } + + /* + * Minimize USB transfers by packing as many commands as possible + * together. If we're not expecting to read, we can assert CS#, write, + * and deassert CS# all in one shot. If reading, we do three separate + * operations. + */ + msg_pspew("Assert CS#\n"); + buf[i++] = SET_BITS_LOW; + buf[i++] = 0 & ~cs_bits; /* assertive */ + buf[i++] = pindir; + + if (writecnt) { + buf[i++] = 0x11; + buf[i++] = (writecnt - 1) & 0xff; + buf[i++] = ((writecnt - 1) >> 8) & 0xff; + memcpy(buf + i, writearr, writecnt); + i += writecnt; + } + + /* + * Optionally terminate this batch of commands with a + * read command, then do the fetch of the results. + */ + if (readcnt) { + buf[i++] = 0x20; + buf[i++] = (readcnt - 1) & 0xff; + buf[i++] = ((readcnt - 1) >> 8) & 0xff; + ret = send_buf(ftdic, buf, i); + failed = ret; + /* We can't abort here, we still have to deassert CS#. */ + if (ret) + msg_perr("send_buf failed before read: %i\n", + ret); + i = 0; + if (ret == 0) { + /* + * FIXME: This is unreliable. There's no guarantee that + * we read the response directly after sending the read + * command. We may be scheduled out etc. + */ + ret = get_buf(ftdic, readarr, readcnt); + failed |= ret; + /* We can't abort here either. */ + if (ret) + msg_perr("get_buf failed: %i\n", ret); + } + } + + msg_pspew("De-assert CS#\n"); + buf[i++] = SET_BITS_LOW; + buf[i++] = cs_bits; + buf[i++] = pindir; + ret = send_buf(ftdic, buf, i); + failed |= ret; + if (ret) + msg_perr("send_buf failed at end: %i\n", ret); + + return failed ? -1 : 0; +} + int ft2232_spi_init(void) { int f; @@ -267,91 +352,6 @@ int ft2232_spi_init(void) return 0; } -int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr) -{ - struct ftdi_context *ftdic = &ftdic_context; - static unsigned char *buf = NULL; - /* failed is special. We use bitwise ops, but it is essentially bool. */ - int i = 0, ret = 0, failed = 0; - int bufsize; - static int oldbufsize = 0; - - if (writecnt > 65536 || readcnt > 65536) - return SPI_INVALID_LENGTH; - - /* buf is not used for the response from the chip. */ - bufsize = max(writecnt + 9, 260 + 9); - /* Never shrink. realloc() calls are expensive. */ - if (bufsize > oldbufsize) { - buf = realloc(buf, bufsize); - if (!buf) { - msg_perr("Out of memory!\n"); - exit(1); - } - oldbufsize = bufsize; - } - - /* - * Minimize USB transfers by packing as many commands as possible - * together. If we're not expecting to read, we can assert CS#, write, - * and deassert CS# all in one shot. If reading, we do three separate - * operations. - */ - msg_pspew("Assert CS#\n"); - buf[i++] = SET_BITS_LOW; - buf[i++] = 0 & ~cs_bits; /* assertive */ - buf[i++] = pindir; - - if (writecnt) { - buf[i++] = 0x11; - buf[i++] = (writecnt - 1) & 0xff; - buf[i++] = ((writecnt - 1) >> 8) & 0xff; - memcpy(buf + i, writearr, writecnt); - i += writecnt; - } - - /* - * Optionally terminate this batch of commands with a - * read command, then do the fetch of the results. - */ - if (readcnt) { - buf[i++] = 0x20; - buf[i++] = (readcnt - 1) & 0xff; - buf[i++] = ((readcnt - 1) >> 8) & 0xff; - ret = send_buf(ftdic, buf, i); - failed = ret; - /* We can't abort here, we still have to deassert CS#. */ - if (ret) - msg_perr("send_buf failed before read: %i\n", - ret); - i = 0; - if (ret == 0) { - /* - * FIXME: This is unreliable. There's no guarantee that - * we read the response directly after sending the read - * command. We may be scheduled out etc. - */ - ret = get_buf(ftdic, readarr, readcnt); - failed |= ret; - /* We can't abort here either. */ - if (ret) - msg_perr("get_buf failed: %i\n", ret); - } - } - - msg_pspew("De-assert CS#\n"); - buf[i++] = SET_BITS_LOW; - buf[i++] = cs_bits; - buf[i++] = pindir; - ret = send_buf(ftdic, buf, i); - failed |= ret; - if (ret) - msg_perr("send_buf failed at end: %i\n", ret); - - return failed ? -1 : 0; -} - void print_supported_usbdevs(const struct usbdev_status *devs) { int i; diff --git a/it85spi.c b/it85spi.c index a388d10..11a2ff5 100644 --- a/it85spi.c +++ b/it85spi.c @@ -226,6 +226,57 @@ void it85xx_exit_scratch_rom() #endif } +/* According to ITE 8502 document, the procedure to follow mode is following: + * 1. write 0x00 to LPC/FWH address 0xffff_fexxh (drive CE# high) + * 2. write data to LPC/FWH address 0xffff_fdxxh (drive CE# low and MOSI + * with data) + * 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get + * data from MISO) + */ +int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + int i; + + it85xx_enter_scratch_rom(); + /* exit scratch rom ONLY when programmer shuts down. Otherwise, the + * temporary flash state may halt EC. */ + +#ifdef LPC_IO + INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); + INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ + INDIRECT_A1(shm_io_base, (((unsigned long int)ce_low) >> 8) & 0xff); +#endif +#ifdef LPC_MEMORY + mmio_writeb(0, ce_high); +#endif + for (i = 0; i < writecnt; ++i) { +#ifdef LPC_IO + INDIRECT_WRITE(shm_io_base, writearr[i]); +#endif +#ifdef LPC_MEMORY + mmio_writeb(writearr[i], ce_low); +#endif + } + for (i = 0; i < readcnt; ++i) { +#ifdef LPC_IO + readarr[i] = INDIRECT_READ(shm_io_base); +#endif +#ifdef LPC_MEMORY + readarr[i] = mmio_readb(ce_low); +#endif + } +#ifdef LPC_IO + INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); + INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ +#endif +#ifdef LPC_MEMORY + mmio_writeb(0, ce_high); +#endif + + return 0; +} + static int it85xx_spi_common_init(struct superio s) { chipaddr base; @@ -295,56 +346,4 @@ int it85xx_shutdown(void) it85xx_exit_scratch_rom(); return 0; } - -/* According to ITE 8502 document, the procedure to follow mode is following: - * 1. write 0x00 to LPC/FWH address 0xffff_fexxh (drive CE# high) - * 2. write data to LPC/FWH address 0xffff_fdxxh (drive CE# low and MOSI - * with data) - * 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get - * data from MISO) - */ -int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr) -{ - int i; - - it85xx_enter_scratch_rom(); - /* exit scratch rom ONLY when programmer shuts down. Otherwise, the - * temporary flash state may halt EC. */ - -#ifdef LPC_IO - INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); - INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ - INDIRECT_A1(shm_io_base, (((unsigned long int)ce_low) >> 8) & 0xff); -#endif -#ifdef LPC_MEMORY - mmio_writeb(0, ce_high); -#endif - for (i = 0; i < writecnt; ++i) { -#ifdef LPC_IO - INDIRECT_WRITE(shm_io_base, writearr[i]); -#endif -#ifdef LPC_MEMORY - mmio_writeb(writearr[i], ce_low); -#endif - } - for (i = 0; i < readcnt; ++i) { -#ifdef LPC_IO - readarr[i] = INDIRECT_READ(shm_io_base); -#endif -#ifdef LPC_MEMORY - readarr[i] = mmio_readb(ce_low); -#endif - } -#ifdef LPC_IO - INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); - INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ -#endif -#ifdef LPC_MEMORY - mmio_writeb(0, ce_high); -#endif - - return 0; -} - #endif diff --git a/it87spi.c b/it87spi.c index 2b09d64..fdf6ccb 100644 --- a/it87spi.c +++ b/it87spi.c @@ -104,127 +104,6 @@ void probe_superio_ite(void) return; } -static uint16_t it87spi_probe(uint16_t port) -{ - uint8_t tmp = 0; - char *portpos = NULL; - uint16_t flashport = 0; - - enter_conf_mode_ite(port); - /* NOLDN, reg 0x24, mask out lowest bit (suspend) */ - tmp = sio_read(port, 0x24) & 0xFE; - /* If IT87SPI was not explicitly selected, we want to check - * quickly if LPC->SPI translation is active. - */ - if ((programmer == PROGRAMMER_INTERNAL) && !(tmp & (0x0E))) { - msg_pdbg("No IT87* serial flash segment enabled.\n"); - exit_conf_mode_ite(port); - /* Nothing to do. */ - return 0; - } - msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", - 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis"); - msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", - 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis"); - msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", - 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis"); - msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", - 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis"); - msg_pdbg("LPC write to serial flash %sabled\n", - (tmp & 1 << 4) ? "en" : "dis"); - /* The LPC->SPI force write enable below only makes sense for - * non-programmer mode. - */ - /* If any serial flash segment is enabled, enable writing. */ - if ((tmp & 0xe) && (!(tmp & 1 << 4))) { - msg_pdbg("Enabling LPC write to serial flash\n"); - tmp |= 1 << 4; - sio_write(port, 0x24, tmp); - } - msg_pdbg("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29); - /* LDN 0x7, reg 0x64/0x65 */ - sio_write(port, 0x07, 0x7); - flashport = sio_read(port, 0x64) << 8; - flashport |= sio_read(port, 0x65); - msg_pdbg("Serial flash port 0x%04x\n", flashport); - /* Non-default port requested? */ - portpos = extract_programmer_param("it87spiport"); - if (portpos) { - char *endptr = NULL; - unsigned long forced_flashport; - forced_flashport = strtoul(portpos, &endptr, 0); - /* Port 0, port >0x1000, unaligned ports and garbage strings - * are rejected. - */ - if (!forced_flashport || (forced_flashport >= 0x1000) || - (forced_flashport & 0x7) || (*endptr != '\0')) { - /* Using ports below 0x100 is a really bad idea, and - * should only be done if no port between 0x100 and - * 0xff8 works due to routing issues. - */ - msg_perr("Error: it87spiport specified, but no valid " - "port specified.\nPort must be a multiple of " - "0x8 and lie between 0x100 and 0xff8.\n"); - free(portpos); - return 1; - } else { - flashport = (uint16_t)forced_flashport; - msg_pinfo("Forcing serial flash port 0x%04x\n", - flashport); - sio_write(port, 0x64, (flashport >> 8)); - sio_write(port, 0x65, (flashport & 0xff)); - } - } - free(portpos); - exit_conf_mode_ite(port); - it8716f_flashport = flashport; - if (buses_supported & CHIP_BUSTYPE_SPI) - msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); - spi_controller = SPI_CONTROLLER_IT87XX; - /* FIXME: Add the SPI bus or replace the other buses with it? */ - buses_supported |= CHIP_BUSTYPE_SPI; - return 0; -} - -int init_superio_ite(void) -{ - int i; - int ret = 0; - - for (i = 0; i < superio_count; i++) { - if (superios[i].vendor != SUPERIO_VENDOR_ITE) - continue; - - switch (superios[i].model) { - case 0x8500: - case 0x8502: - case 0x8510: - case 0x8511: - case 0x8512: - /* FIXME: This should be enabled, but we need a check - * for laptop whitelisting due to the amount of things - * which can go wrong if the EC firmware does not - * implement the interface we want. - */ - //it85xx_spi_init(superios[i]); - break; - case 0x8705: - ret |= it8705f_write_enable(superios[i].port); - break; - case 0x8716: - case 0x8718: - case 0x8720: - ret |= it87spi_probe(superios[i].port); - break; - default: - msg_pdbg("Super I/O ID 0x%04hx is not on the list of " - "flash capable controllers.\n", - superios[i].model); - } - } - return ret; -} - /* * The IT8716F only supports commands with length 1,2,4,5 bytes including * command byte and can not read more than 3 bytes from the device. @@ -386,4 +265,125 @@ int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, return 0; } +static uint16_t it87spi_probe(uint16_t port) +{ + uint8_t tmp = 0; + char *portpos = NULL; + uint16_t flashport = 0; + + enter_conf_mode_ite(port); + /* NOLDN, reg 0x24, mask out lowest bit (suspend) */ + tmp = sio_read(port, 0x24) & 0xFE; + /* If IT87SPI was not explicitly selected, we want to check + * quickly if LPC->SPI translation is active. + */ + if ((programmer == PROGRAMMER_INTERNAL) && !(tmp & (0x0E))) { + msg_pdbg("No IT87* serial flash segment enabled.\n"); + exit_conf_mode_ite(port); + /* Nothing to do. */ + return 0; + } + msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis"); + msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis"); + msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis"); + msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis"); + msg_pdbg("LPC write to serial flash %sabled\n", + (tmp & 1 << 4) ? "en" : "dis"); + /* The LPC->SPI force write enable below only makes sense for + * non-programmer mode. + */ + /* If any serial flash segment is enabled, enable writing. */ + if ((tmp & 0xe) && (!(tmp & 1 << 4))) { + msg_pdbg("Enabling LPC write to serial flash\n"); + tmp |= 1 << 4; + sio_write(port, 0x24, tmp); + } + msg_pdbg("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29); + /* LDN 0x7, reg 0x64/0x65 */ + sio_write(port, 0x07, 0x7); + flashport = sio_read(port, 0x64) << 8; + flashport |= sio_read(port, 0x65); + msg_pdbg("Serial flash port 0x%04x\n", flashport); + /* Non-default port requested? */ + portpos = extract_programmer_param("it87spiport"); + if (portpos) { + char *endptr = NULL; + unsigned long forced_flashport; + forced_flashport = strtoul(portpos, &endptr, 0); + /* Port 0, port >0x1000, unaligned ports and garbage strings + * are rejected. + */ + if (!forced_flashport || (forced_flashport >= 0x1000) || + (forced_flashport & 0x7) || (*endptr != '\0')) { + /* Using ports below 0x100 is a really bad idea, and + * should only be done if no port between 0x100 and + * 0xff8 works due to routing issues. + */ + msg_perr("Error: it87spiport specified, but no valid " + "port specified.\nPort must be a multiple of " + "0x8 and lie between 0x100 and 0xff8.\n"); + free(portpos); + return 1; + } else { + flashport = (uint16_t)forced_flashport; + msg_pinfo("Forcing serial flash port 0x%04x\n", + flashport); + sio_write(port, 0x64, (flashport >> 8)); + sio_write(port, 0x65, (flashport & 0xff)); + } + } + free(portpos); + exit_conf_mode_ite(port); + it8716f_flashport = flashport; + if (buses_supported & CHIP_BUSTYPE_SPI) + msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); + spi_controller = SPI_CONTROLLER_IT87XX; + /* FIXME: Add the SPI bus or replace the other buses with it? */ + buses_supported |= CHIP_BUSTYPE_SPI; + return 0; +} + +int init_superio_ite(void) +{ + int i; + int ret = 0; + + for (i = 0; i < superio_count; i++) { + if (superios[i].vendor != SUPERIO_VENDOR_ITE) + continue; + + switch (superios[i].model) { + case 0x8500: + case 0x8502: + case 0x8510: + case 0x8511: + case 0x8512: + /* FIXME: This should be enabled, but we need a check + * for laptop whitelisting due to the amount of things + * which can go wrong if the EC firmware does not + * implement the interface we want. + */ + //it85xx_spi_init(superios[i]); + break; + case 0x8705: + ret |= it8705f_write_enable(superios[i].port); + break; + case 0x8716: + case 0x8718: + case 0x8720: + ret |= it87spi_probe(superios[i].port); + break; + default: + msg_pdbg("Super I/O ID 0x%04hx is not on the list of " + "flash capable controllers.\n", + superios[i].model); + } + } + return ret; +} + #endif diff --git a/wbsio_spi.c b/wbsio_spi.c index acf9cb2..12c458e 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -30,53 +30,6 @@ static uint16_t wbsio_spibase = 0; -static uint16_t wbsio_get_spibase(uint16_t port) -{ - uint8_t id; - uint16_t flashport = 0; - - w836xx_ext_enter(port); - id = sio_read(port, 0x20); - if (id != 0xa0) { - msg_perr("\nW83627 not found at 0x%x, id=0x%02x want=0xa0.\n", port, id); - goto done; - } - - if (0 == (sio_read(port, 0x24) & 2)) { - msg_perr("\nW83627 found at 0x%x, but SPI pins are not enabled. (CR[0x24] bit 1=0)\n", port); - goto done; - } - - sio_write(port, 0x07, 0x06); - if (0 == (sio_read(port, 0x30) & 1)) { - msg_perr("\nW83627 found at 0x%x, but SPI is not enabled. (LDN6[0x30] bit 0=0)\n", port); - goto done; - } - - flashport = (sio_read(port, 0x62) << 8) | sio_read(port, 0x63); - -done: - w836xx_ext_leave(port); - return flashport; -} - -int wbsio_check_for_spi(void) -{ - if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1))) - if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2))) - return 1; - - msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); - - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_WBSIO; - msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " - "1024 KB!\n", __func__); - max_rom_decode.spi = 1024 * 1024; - - return 0; -} - /* W83627DHG has 11 command modes: * 1=1 command only * 2=1 command+1 data write @@ -186,4 +139,51 @@ int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) return read_memmapped(flash, buf, start, len); } +static uint16_t wbsio_get_spibase(uint16_t port) +{ + uint8_t id; + uint16_t flashport = 0; + + w836xx_ext_enter(port); + id = sio_read(port, 0x20); + if (id != 0xa0) { + msg_perr("\nW83627 not found at 0x%x, id=0x%02x want=0xa0.\n", port, id); + goto done; + } + + if (0 == (sio_read(port, 0x24) & 2)) { + msg_perr("\nW83627 found at 0x%x, but SPI pins are not enabled. (CR[0x24] bit 1=0)\n", port); + goto done; + } + + sio_write(port, 0x07, 0x06); + if (0 == (sio_read(port, 0x30) & 1)) { + msg_perr("\nW83627 found at 0x%x, but SPI is not enabled. (LDN6[0x30] bit 0=0)\n", port); + goto done; + } + + flashport = (sio_read(port, 0x62) << 8) | sio_read(port, 0x63); + +done: + w836xx_ext_leave(port); + return flashport; +} + +int wbsio_check_for_spi(void) +{ + if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1))) + if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2))) + return 1; + + msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); + + buses_supported |= CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_WBSIO; + msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " + "1024 KB!\n", __func__); + max_rom_decode.spi = 1024 * 1024; + + return 0; +} + #endif -- 1.7.4.1

1 0

[PATCH 1/3] Factor out SPI write/read chunking wrappers.
by Michael Karcher 04 May '11

04 May '11

Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- bitbang_spi.c | 11 ------ buspirate_spi.c | 10 ----- dummyflasher.c | 6 --- ft2232_spi.c | 11 ------ ichspi.c | 20 ----------- it85spi.c | 10 ----- programmer.h | 21 ++++------- sb600spi.c | 11 ------ spi.c | 102 ++++++++++++++++++++++++++++++++++++++++++------------ 9 files changed, 87 insertions(+), 115 deletions(-) diff --git a/bitbang_spi.c b/bitbang_spi.c index fb404ac..d63c769 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -151,14 +151,3 @@ int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } - -int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - /* Maximum read length is unlimited, use 64k bytes. */ - return spi_read_chunked(flash, buf, start, len, 64 * 1024); -} - -int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - return spi_write_chunked(flash, buf, start, len, 256); -} diff --git a/buspirate_spi.c b/buspirate_spi.c index d24f890..e7a7a10 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -326,13 +326,3 @@ int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, return ret; } - -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - return spi_read_chunked(flash, buf, start, len, 12); -} - -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - return spi_write_chunked(flash, buf, start, len, 12); -} diff --git a/dummyflasher.c b/dummyflasher.c index d818a84..b6e67db 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -507,12 +507,6 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - /* Maximum read length is unlimited, use 64kB. */ - return spi_read_chunked(flash, buf, start, len, 64 * 1024); -} - int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, diff --git a/ft2232_spi.c b/ft2232_spi.c index 7373624..7ff1d81 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -352,17 +352,6 @@ int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, return failed ? -1 : 0; } -int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - /* Maximum read length is 64k bytes. */ - return spi_read_chunked(flash, buf, start, len, 64 * 1024); -} - -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - return spi_write_chunked(flash, buf, start, len, 256); -} - void print_supported_usbdevs(const struct usbdev_status *devs) { int i; diff --git a/ichspi.c b/ichspi.c index f2814d1..4315e78 100644 --- a/ichspi.c +++ b/ichspi.c @@ -834,26 +834,6 @@ static int run_opcode(OPCODE op, uint32_t offset, return -1; } -int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) -{ - int maxdata = 64; - - if (spi_controller == SPI_CONTROLLER_VIA) - maxdata = 16; - - return spi_read_chunked(flash, buf, start, len, maxdata); -} - -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) -{ - int maxdata = 64; - - if (spi_controller == SPI_CONTROLLER_VIA) - maxdata = 16; - - return spi_write_chunked(flash, buf, start, len, maxdata); -} - int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { diff --git a/it85spi.c b/it85spi.c index 1710d8e..a388d10 100644 --- a/it85spi.c +++ b/it85spi.c @@ -347,14 +347,4 @@ int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } -int it85_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) -{ - return spi_read_chunked(flash, buf, start, len, 64); -} - -int it85_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) -{ - return spi_write_chunked(flash, buf, start, len, 64); -} - #endif diff --git a/programmer.h b/programmer.h index 19c3a30..fefb9cd 100644 --- a/programmer.h +++ b/programmer.h @@ -358,7 +358,6 @@ uint32_t dummy_chip_readl(const chipaddr addr); void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); #endif @@ -462,8 +461,6 @@ struct usbdev_status { }; int ft2232_spi_init(void); int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); extern const struct usbdev_status devs_ft2232spi[]; void print_supported_usbdevs(const struct usbdev_status *devs); #endif @@ -484,8 +481,6 @@ int mcp6x_spi_init(int want_spi); int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); int bitbang_spi_shutdown(const struct bitbang_spi_master *master); int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* buspirate_spi.c */ struct buspirate_spispeeds { @@ -495,8 +490,6 @@ struct buspirate_spispeeds { int buspirate_spi_init(void); int buspirate_spi_shutdown(void); int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* dediprog.c */ int dediprog_init(void); @@ -561,7 +554,13 @@ enum spi_controller { SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; extern const int spi_programmer_count; + +#define MAX_DATA_UNSPECIFIED 0 +#define MAX_DATA_READ_UNLIMITED 64 * 1024 +#define MAX_DATA_WRITE_UNLIMITED 256 struct spi_programmer { + int max_data_read; + int max_data_write; int (*command)(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int (*multicommand)(struct spi_command *cmds); @@ -576,6 +575,8 @@ extern const struct spi_programmer spi_programmer[]; int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int default_spi_send_multicommand(struct spi_command *cmds); +int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* ichspi.c */ #if CONFIG_INTERNAL == 1 @@ -585,8 +586,6 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int via_init_spi(struct pci_dev *dev); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); int ich_spi_send_multicommand(struct spi_command *cmds); #endif @@ -595,8 +594,6 @@ int it85xx_spi_init(struct superio s); int it85xx_shutdown(void); int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int it85_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len); -int it85_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); /* it87spi.c */ void enter_conf_mode_ite(uint16_t port); @@ -613,8 +610,6 @@ int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int sb600_probe_spi(struct pci_dev *dev); int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* wbsio_spi.c */ diff --git a/sb600spi.c b/sb600spi.c index 845cf58..269af8a 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -43,17 +43,6 @@ static uint8_t *sb600_spibar = NULL; -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - /* Maximum read length is 8 bytes. */ - return spi_read_chunked(flash, buf, start, len, 8); -} - -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) -{ - return spi_write_chunked(flash, buf, start, len, 5); -} - static void reset_internal_fifo_pointer(void) { mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2); diff --git a/spi.c b/spi.c index 7e9ff1a..5857fda 100644 --- a/spi.c +++ b/spi.c @@ -34,6 +34,8 @@ enum spi_controller spi_controller = SPI_CONTROLLER_NONE; const struct spi_programmer spi_programmer[] = { { /* SPI_CONTROLLER_NONE */ + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, .command = NULL, .multicommand = NULL, .read = NULL, @@ -43,27 +45,35 @@ const struct spi_programmer spi_programmer[] = { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) { /* SPI_CONTROLLER_ICH7 */ + .max_data_read = 64, + .max_data_write = 64, .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, { /* SPI_CONTROLLER_ICH9 */ + .max_data_read = 64, + .max_data_write = 64, .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, { /* SPI_CONTROLLER_IT85XX */ + .max_data_read = 64, + .max_data_write = 64, .command = it85xx_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = it85_spi_read, - .write_256 = it85_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, { /* SPI_CONTROLLER_IT87XX */ + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, .command = it8716f_spi_send_command, .multicommand = default_spi_send_multicommand, .read = it8716f_spi_chip_read, @@ -71,20 +81,26 @@ const struct spi_programmer spi_programmer[] = { }, { /* SPI_CONTROLLER_SB600 */ + .max_data_read = 8, + .max_data_write = 5, .command = sb600_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = sb600_spi_read, - .write_256 = sb600_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, { /* SPI_CONTROLLER_VIA */ + .max_data_read = 16, + .max_data_write = 16, .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, { /* SPI_CONTROLLER_WBSIO */ + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, .command = wbsio_spi_send_command, .multicommand = default_spi_send_multicommand, .read = wbsio_spi_read, @@ -92,43 +108,53 @@ const struct spi_programmer spi_programmer[] = { }, { /* SPI_CONTROLLER_MCP6X_BITBANG */ + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, .command = bitbang_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = bitbang_spi_read, - .write_256 = bitbang_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif #endif #if CONFIG_FT2232_SPI == 1 { /* SPI_CONTROLLER_FT2232 */ + .max_data_read = 64 * 1024, + .max_data_write = 256, .command = ft2232_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = ft2232_spi_read, - .write_256 = ft2232_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif #if CONFIG_DUMMY == 1 { /* SPI_CONTROLLER_DUMMY */ + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_UNSPECIFIED, .command = dummy_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = dummy_spi_read, + .read = default_spi_read, .write_256 = dummy_spi_write_256, }, #endif #if CONFIG_BUSPIRATE_SPI == 1 { /* SPI_CONTROLLER_BUSPIRATE */ + .max_data_read = 12, + .max_data_write = 12, .command = buspirate_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = buspirate_spi_read, - .write_256 = buspirate_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif #if CONFIG_DEDIPROG == 1 { /* SPI_CONTROLLER_DEDIPROG */ + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, .command = dediprog_spi_send_command, .multicommand = default_spi_send_multicommand, .read = dediprog_spi_read, @@ -138,28 +164,34 @@ const struct spi_programmer spi_programmer[] = { #if CONFIG_RAYER_SPI == 1 { /* SPI_CONTROLLER_RAYER */ + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, .command = bitbang_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = bitbang_spi_read, - .write_256 = bitbang_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif #if CONFIG_NICINTEL_SPI == 1 { /* SPI_CONTROLLER_NICINTEL */ + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, .command = bitbang_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = bitbang_spi_read, - .write_256 = bitbang_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif #if CONFIG_OGP_SPI == 1 { /* SPI_CONTROLLER_OGP */ + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, .command = bitbang_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = bitbang_spi_read, - .write_256 = bitbang_spi_write_256, + .read = default_spi_read, + .write_256 = default_spi_write_256, }, #endif @@ -223,6 +255,30 @@ int default_spi_send_multicommand(struct spi_command *cmds) return result; } +int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + int max_data = spi_programmer[spi_controller].max_data_read; + if (max_data == MAX_DATA_UNSPECIFIED) { + msg_perr("%s called, but SPI read chunk size not defined " + "on this hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); + return 1; + } + return spi_read_chunked(flash, buf, start, len, max_data); +} + +int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + int max_data = spi_programmer[spi_controller].max_data_write; + if (max_data == MAX_DATA_UNSPECIFIED) { + msg_perr("%s called, but SPI write chunk size not defined " + "on this hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); + return 1; + } + return spi_write_chunked(flash, buf, start, len, max_data); +} + int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int addrbase = 0; -- 1.7.4.1

1 0

Problem G41MXE Foxconn
by Marcelo Sales Moreira 04 May '11

04 May '11

Good morning, I am having problem with the motherboard model G41MXE - DDR3 Foxconn, I wonder if there any solution to solve this problem. Attached file with the information with command flashrom -V Att Marcelo Moreira Sales

2 1

jmiteff flashrom -V output
by jmiteff＠charter.net 04 May '11

04 May '11

1 0

FAILED; K9N PLATINUM A7250NMS
by jmiteff＠charter.net 04 May '11

04 May '11

Help, it failed. Says that erase failed at 0x000165c0

1 0

FAILED; k9n a7250nms platinum
by jmiteff＠charter.net 04 May '11

04 May '11

Help, the bios flash failed. Program says not to reboot or shutdown. What do I do next? Have I lost my motherboard?

1 0

RFC: precious regions
by Michael Karcher 04 May '11

04 May '11

Hello flashrom developers, INTRO (may be skipped): ----------------------- while I know that I should spend my time for flashrom with polishing my patches instead of proposing even more changes, I need to write down the idea about "precious regions", as we had two incidentes of descriptor-mode ICH southbridges recently. Some of them would have been prevented by using current HEAD, but even svn HEAD is able to some destruct typical descriptor mode systems. Imagine: Descriptor: 0-8K (r/o) Gigabit: 8K-32K (r/w) BIOS: 32K-2M (r/w) flashrom HEAD will first read the whole chip, then try to erase. All block erase instructions will fail, as the descriptor is r/o. But the chip erase instruction still can be sucessfully sent, and erase verification works, too. In the last step, the new image gets written - but not to the descriptor, as that on is R/O. IDEA: ----- Introduce the concept of "precious regions", i.e. parts of the flash chip that may never be erased. Flashrom would deny to send erase commands to blocks that overlap with precious regions. This might cause flashrom to fail in certain cases where a block that crosses a border between precious and non-precios needs to be erased to modify the contents of the non-precious region, so "precious regions" should not be overused (i.e. declare all not-to-be-modified regions from the layout file as "precious" unconditionally). I see the main use case for precious regions in these two items: - Regions we know we can't write, because of the flash firewall in the chipset. Most flash chips implement their locks in a way that a non-programmable area is non-eraseable, so flash chip locks don't need the "erase forbidden" handling. - Embedded controller code and boot block code precious regions for unwritable areas are mandatory, as flashrom will leave a messed up system behind otherwise, while precious regions for boot block and EC code of course should be optional, but are very nice to have as safety net on computers with soldered flash. I explicitly don't suggest trying to implement a general algorithm to find boot block and EC code in vendor images in flashrom, but a 3rd-party tool to generate layout files might be nice. I do think of extending layout file syntax to be able to flag layout parts (e.g. as precious, but other flags like "prefer big erase/prefer small erase" might make sense too), though. What are your thoughts about this? BACKUP IDEA: ------------ If the precious region stuff seems as overdesigned, we should abort as soon as we find any non-rw region on the ichspi driver. Regards, Michael Karcher

2 3

[PATCH] Constify flashchips array
by Carl-Daniel Hailfinger 03 May '11

03 May '11

Constify flashchips array. This moves 99.5% of the .data section to .rodata (which ends up in .text). Disadvantages: We have one additional memcpy with sizeof(struct flashchip) per executed probe. This is purely startup cost and won't have any impact on operation after probing. Tests would be appreciated, especially with machines having multiple chips. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-const_flashchips/flash.h =================================================================== --- flashrom-const_flashchips/flash.h (Revision 1252) +++ flashrom-const_flashchips/flash.h (Arbeitskopie) @@ -173,7 +173,7 @@ #define TIMING_IGNORED -1 #define TIMING_ZERO -2 -extern struct flashchip flashchips[]; +extern const struct flashchip flashchips[]; /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); @@ -193,7 +193,7 @@ void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); int erase_flash(struct flashchip *flash); -struct flashchip *probe_flash(struct flashchip *first_flash, int force); +int probe_flash(int startchip, struct flashchip *fill_flash, int force); int read_flash_to_file(struct flashchip *flash, char *filename); int min(int a, int b); int max(int a, int b); Index: flashrom-const_flashchips/cli_classic.c =================================================================== --- flashrom-const_flashchips/cli_classic.c (Revision 1252) +++ flashrom-const_flashchips/cli_classic.c (Arbeitskopie) @@ -100,7 +100,11 @@ { unsigned long size; /* Probe for up to three flash chips. */ - struct flashchip *flash, *flashes[3]; + const struct flashchip *flash; + struct flashchip flashes[3]; + struct flashchip *fill_flash; + int startchip = 0; + int chipcount = 0; const char *name; int namelen; int opt; @@ -359,49 +363,47 @@ exit(1); } - /* FIXME: Delay calibration should happen in programmer code. */ for (i = 0; i < ARRAY_SIZE(flashes); i++) { - flashes[i] = - probe_flash(i ? flashes[i - 1] + 1 : flashchips, 0); - if (!flashes[i]) - for (i++; i < ARRAY_SIZE(flashes); i++) - flashes[i] = NULL; + startchip = probe_flash(startchip, &flashes[i], 0); + if (startchip == -1) + break; + chipcount++; } - if (flashes[1]) { + if (chipcount > 1) { printf("Multiple flash chips were detected:"); - for (i = 0; i < ARRAY_SIZE(flashes) && flashes[i]; i++) - printf(" %s", flashes[i]->name); + for (i = 0; i < chipcount; i++) + printf(" %s", flashes[i].name); printf("\nPlease specify which chip to use with the -c <chipname> option.\n"); programmer_shutdown(); exit(1); - } else if (!flashes[0]) { + } else if (!chipcount) { printf("No EEPROM/flash device found.\n"); if (!force || !chip_to_probe) { printf("Note: flashrom can never write if the flash chip isn't found automatically.\n"); } if (force && read_it && chip_to_probe) { printf("Force read (-f -r -c) requested, pretending the chip is there:\n"); - flashes[0] = probe_flash(flashchips, 1); - if (!flashes[0]) { + startchip = probe_flash(0, &flashes[0], 1); + if (startchip == -1) { printf("Probing for flash chip '%s' failed.\n", chip_to_probe); programmer_shutdown(); exit(1); } printf("Please note that forced reads most likely contain garbage.\n"); - return read_flash_to_file(flashes[0], filename); + return read_flash_to_file(&flashes[0], filename); } // FIXME: flash writes stay enabled! programmer_shutdown(); exit(1); } - flash = flashes[0]; + fill_flash = &flashes[0]; - check_chip_supported(flash); + check_chip_supported(fill_flash); - size = flash->total_size * 1024; - if (check_max_decode((buses_supported & flash->bustype), size) && + size = fill_flash->total_size * 1024; + if (check_max_decode((buses_supported & fill_flash->bustype), size) && (!force)) { fprintf(stderr, "Chip is too big for this programmer " "(-V gives details). Use --force to override.\n"); @@ -432,5 +434,5 @@ * Give the chip time to settle. */ programmer_delay(100000); - return doit(flash, force, filename, read_it, write_it, erase_it, verify_it); + return doit(fill_flash, force, filename, read_it, write_it, erase_it, verify_it); } Index: flashrom-const_flashchips/print_wiki.c =================================================================== --- flashrom-const_flashchips/print_wiki.c (Revision 1252) +++ flashrom-const_flashchips/print_wiki.c (Arbeitskopie) @@ -201,7 +201,7 @@ static void print_supported_chips_wiki(int cols) { int i = 0, c = 1, chipcount = 0; - struct flashchip *f, *old = NULL; + const struct flashchip *f, *old = NULL; uint32_t t; for (f = flashchips; f->name != NULL; f++) Index: flashrom-const_flashchips/flashchips.c =================================================================== --- flashrom-const_flashchips/flashchips.c (Revision 1252) +++ flashrom-const_flashchips/flashchips.c (Arbeitskopie) @@ -32,7 +32,7 @@ * Please keep the list sorted by vendor name and chip name, so that * the output of 'flashrom -L' is alphabetically sorted. */ -struct flashchip flashchips[] = { +const struct flashchip flashchips[] = { /* * .vendor = Vendor name Index: flashrom-const_flashchips/flashrom.c =================================================================== --- flashrom-const_flashchips/flashrom.c (Revision 1252) +++ flashrom-const_flashchips/flashrom.c (Arbeitskopie) @@ -1123,15 +1123,15 @@ return 1; } -struct flashchip *probe_flash(struct flashchip *first_flash, int force) +int probe_flash(int startchip, struct flashchip *fill_flash, int force) { - struct flashchip *flash; + const struct flashchip *flash; unsigned long base = 0; uint32_t size; enum chipbustype buses_common; char *tmp; - for (flash = first_flash; flash && flash->name; flash++) { + for (flash = flashchips + startchip; flash && flash->name; flash++) { if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0) continue; msg_gdbg("Probing for %s %s, %d KB: ", @@ -1158,25 +1158,35 @@ size = flash->total_size * 1024; check_max_decode(buses_common, size); + /* Start filling in the dynamic data. */ + *fill_flash = *flash; + base = flashbase ? flashbase : (0xffffffff - size + 1); - flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); + fill_flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); if (force) break; - if (flash->probe(flash) != 1) + if (fill_flash->probe(fill_flash) != 1) goto notfound; - if (first_flash == flashchips - || flash->model_id != GENERIC_DEVICE_ID) + /* If this is the first chip found, accept it. + * If this is not the first chip found, accept it only if it is + * a non-generic match. + * We could either make chipcount global or provide it as + * parameter, or we assume that startchip==0 means this call to + * probe_flash() is the first one and thus no chip has been + * found before. + */ + if (startchip == 0 || fill_flash->model_id != GENERIC_DEVICE_ID) break; notfound: - programmer_unmap_flash_region((void *)flash->virtual_memory, size); + programmer_unmap_flash_region((void *)fill_flash->virtual_memory, size); } if (!flash || !flash->name) - return NULL; + return -1; msg_cinfo("%s chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n", force ? "Assuming" : "Found", @@ -1187,10 +1197,11 @@ * may be stored in registers, so avoid lock info printing. */ if (!force) - if (flash->printlock) - flash->printlock(flash); + if (fill_flash->printlock) + fill_flash->printlock(fill_flash); - return flash; + /* Return position of matching chip. */ + return flash - flashchips; } int verify_flash(struct flashchip *flash, uint8_t *buf) @@ -1299,7 +1310,7 @@ * walk_eraseregions(). * Even if an error is found, the function will keep going and check the rest. */ -static int selfcheck_eraseblocks(struct flashchip *flash) +static int selfcheck_eraseblocks(const struct flashchip *flash) { int i, j, k; int ret = 0; @@ -1676,7 +1687,7 @@ int selfcheck(void) { int ret = 0; - struct flashchip *flash; + const struct flashchip *flash; /* Safety check. Instead of aborting after the first error, check * if more errors exist. @@ -1695,7 +1706,7 @@ return ret; } -void check_chip_supported(struct flashchip *flash) +void check_chip_supported(const struct flashchip *flash) { if (TEST_OK_MASK != (flash->tested & TEST_OK_MASK)) { msg_cinfo("===\n"); Index: flashrom-const_flashchips/programmer.h =================================================================== --- flashrom-const_flashchips/programmer.h (Revision 1252) +++ flashrom-const_flashchips/programmer.h (Arbeitskopie) @@ -497,7 +497,7 @@ extern struct decode_sizes max_rom_decode; extern int programmer_may_write; extern unsigned long flashbase; -void check_chip_supported(struct flashchip *flash); +void check_chip_supported(const struct flashchip *flash); int check_max_decode(enum chipbustype buses, uint32_t size); char *extract_programmer_param(char *param_name); Index: flashrom-const_flashchips/print.c =================================================================== --- flashrom-const_flashchips/print.c (Revision 1252) +++ flashrom-const_flashchips/print.c (Arbeitskopie) @@ -78,7 +78,7 @@ { int okcol = 0, pos = 0, i, chipcount = 0; int maxchiplen = 0, maxvendorlen = 0; - struct flashchip *f; + const struct flashchip *f; for (f = flashchips; f->name != NULL; f++) { /* Ignore "unknown XXXX SPI chip" entries. */ -- http://www.hailfinger.org/

3 7

[commit] r1293 - trunk
by repository service 03 May '11

03 May '11

Author: hailfinger Date: Wed May 4 02:39:50 2011 New Revision: 1293 URL: http://flashrom.org/trac/flashrom/changeset/1293 Log: Constify flashchips array. This moves 99.5% of the .data section to .rodata (which ends up in .text). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/cli_classic.c trunk/flash.h trunk/flashchips.c trunk/flashrom.c trunk/print.c trunk/print_wiki.c trunk/programmer.h Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Tue May 3 23:49:41 2011 (r1292) +++ trunk/cli_classic.c Wed May 4 02:39:50 2011 (r1293) @@ -100,7 +100,11 @@ { unsigned long size; /* Probe for up to three flash chips. */ - struct flashchip *flash, *flashes[3]; + const struct flashchip *flash; + struct flashchip flashes[3]; + struct flashchip *fill_flash; + int startchip = 0; + int chipcount = 0; const char *name; int namelen; int opt; @@ -359,49 +363,47 @@ exit(1); } - /* FIXME: Delay calibration should happen in programmer code. */ for (i = 0; i < ARRAY_SIZE(flashes); i++) { - flashes[i] = - probe_flash(i ? flashes[i - 1] + 1 : flashchips, 0); - if (!flashes[i]) - for (i++; i < ARRAY_SIZE(flashes); i++) - flashes[i] = NULL; + startchip = probe_flash(startchip, &flashes[i], 0); + if (startchip == -1) + break; + chipcount++; } - if (flashes[1]) { + if (chipcount > 1) { printf("Multiple flash chips were detected:"); - for (i = 0; i < ARRAY_SIZE(flashes) && flashes[i]; i++) - printf(" %s", flashes[i]->name); + for (i = 0; i < chipcount; i++) + printf(" %s", flashes[i].name); printf("\nPlease specify which chip to use with the -c <chipname> option.\n"); programmer_shutdown(); exit(1); - } else if (!flashes[0]) { + } else if (!chipcount) { printf("No EEPROM/flash device found.\n"); if (!force || !chip_to_probe) { printf("Note: flashrom can never write if the flash chip isn't found automatically.\n"); } if (force && read_it && chip_to_probe) { printf("Force read (-f -r -c) requested, pretending the chip is there:\n"); - flashes[0] = probe_flash(flashchips, 1); - if (!flashes[0]) { + startchip = probe_flash(0, &flashes[0], 1); + if (startchip == -1) { printf("Probing for flash chip '%s' failed.\n", chip_to_probe); programmer_shutdown(); exit(1); } printf("Please note that forced reads most likely contain garbage.\n"); - return read_flash_to_file(flashes[0], filename); + return read_flash_to_file(&flashes[0], filename); } // FIXME: flash writes stay enabled! programmer_shutdown(); exit(1); } - flash = flashes[0]; + fill_flash = &flashes[0]; - check_chip_supported(flash); + check_chip_supported(fill_flash); - size = flash->total_size * 1024; - if (check_max_decode((buses_supported & flash->bustype), size) && + size = fill_flash->total_size * 1024; + if (check_max_decode((buses_supported & fill_flash->bustype), size) && (!force)) { fprintf(stderr, "Chip is too big for this programmer " "(-V gives details). Use --force to override.\n"); @@ -432,5 +434,5 @@ * Give the chip time to settle. */ programmer_delay(100000); - return doit(flash, force, filename, read_it, write_it, erase_it, verify_it); + return doit(fill_flash, force, filename, read_it, write_it, erase_it, verify_it); } Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Tue May 3 23:49:41 2011 (r1292) +++ trunk/flash.h Wed May 4 02:39:50 2011 (r1293) @@ -173,7 +173,7 @@ #define TIMING_IGNORED -1 #define TIMING_ZERO -2 -extern struct flashchip flashchips[]; +extern const struct flashchip flashchips[]; /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); @@ -193,7 +193,7 @@ void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); int erase_flash(struct flashchip *flash); -struct flashchip *probe_flash(struct flashchip *first_flash, int force); +int probe_flash(int startchip, struct flashchip *fill_flash, int force); int read_flash_to_file(struct flashchip *flash, char *filename); int min(int a, int b); int max(int a, int b); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Tue May 3 23:49:41 2011 (r1292) +++ trunk/flashchips.c Wed May 4 02:39:50 2011 (r1293) @@ -32,7 +32,7 @@ * Please keep the list sorted by vendor name and chip name, so that * the output of 'flashrom -L' is alphabetically sorted. */ -struct flashchip flashchips[] = { +const struct flashchip flashchips[] = { /* * .vendor = Vendor name Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Tue May 3 23:49:41 2011 (r1292) +++ trunk/flashrom.c Wed May 4 02:39:50 2011 (r1293) @@ -1109,16 +1109,16 @@ return 1; } -struct flashchip *probe_flash(struct flashchip *first_flash, int force) +int probe_flash(int startchip, struct flashchip *fill_flash, int force) { - struct flashchip *flash; + const struct flashchip *flash; unsigned long base = 0; char location[64]; uint32_t size; enum chipbustype buses_common; char *tmp; - for (flash = first_flash; flash && flash->name; flash++) { + for (flash = flashchips + startchip; flash && flash->name; flash++) { if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0) continue; msg_gdbg("Probing for %s %s, %d KB: ", @@ -1145,25 +1145,35 @@ size = flash->total_size * 1024; check_max_decode(buses_common, size); + /* Start filling in the dynamic data. */ + *fill_flash = *flash; + base = flashbase ? flashbase : (0xffffffff - size + 1); - flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); + fill_flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); if (force) break; - if (flash->probe(flash) != 1) + if (fill_flash->probe(fill_flash) != 1) goto notfound; - if (first_flash == flashchips - || flash->model_id != GENERIC_DEVICE_ID) + /* If this is the first chip found, accept it. + * If this is not the first chip found, accept it only if it is + * a non-generic match. + * We could either make chipcount global or provide it as + * parameter, or we assume that startchip==0 means this call to + * probe_flash() is the first one and thus no chip has been + * found before. + */ + if (startchip == 0 || fill_flash->model_id != GENERIC_DEVICE_ID) break; notfound: - programmer_unmap_flash_region((void *)flash->virtual_memory, size); + programmer_unmap_flash_region((void *)fill_flash->virtual_memory, size); } if (!flash || !flash->name) - return NULL; + return -1; #if CONFIG_INTERNAL == 1 if (programmer_table[programmer].map_flash_region == physmap) @@ -1181,10 +1191,11 @@ * may be stored in registers, so avoid lock info printing. */ if (!force) - if (flash->printlock) - flash->printlock(flash); + if (fill_flash->printlock) + fill_flash->printlock(fill_flash); - return flash; + /* Return position of matching chip. */ + return flash - flashchips; } int verify_flash(struct flashchip *flash, uint8_t *buf) @@ -1293,7 +1304,7 @@ * walk_eraseregions(). * Even if an error is found, the function will keep going and check the rest. */ -static int selfcheck_eraseblocks(struct flashchip *flash) +static int selfcheck_eraseblocks(const struct flashchip *flash) { int i, j, k; int ret = 0; @@ -1670,7 +1681,7 @@ int selfcheck(void) { int ret = 0; - struct flashchip *flash; + const struct flashchip *flash; /* Safety check. Instead of aborting after the first error, check * if more errors exist. @@ -1689,7 +1700,7 @@ return ret; } -void check_chip_supported(struct flashchip *flash) +void check_chip_supported(const struct flashchip *flash) { if (TEST_OK_MASK != (flash->tested & TEST_OK_MASK)) { msg_cinfo("===\n"); Modified: trunk/print.c ============================================================================== --- trunk/print.c Tue May 3 23:49:41 2011 (r1292) +++ trunk/print.c Wed May 4 02:39:50 2011 (r1293) @@ -78,7 +78,7 @@ { int okcol = 0, pos = 0, i, chipcount = 0; int maxchiplen = 0, maxvendorlen = 0; - struct flashchip *f; + const struct flashchip *f; for (f = flashchips; f->name != NULL; f++) { /* Ignore "unknown XXXX SPI chip" entries. */ Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Tue May 3 23:49:41 2011 (r1292) +++ trunk/print_wiki.c Wed May 4 02:39:50 2011 (r1293) @@ -201,7 +201,7 @@ static void print_supported_chips_wiki(int cols) { int i = 0, c = 1, chipcount = 0; - struct flashchip *f, *old = NULL; + const struct flashchip *f, *old = NULL; uint32_t t; for (f = flashchips; f->name != NULL; f++) Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Tue May 3 23:49:41 2011 (r1292) +++ trunk/programmer.h Wed May 4 02:39:50 2011 (r1293) @@ -515,7 +515,7 @@ extern struct decode_sizes max_rom_decode; extern int programmer_may_write; extern unsigned long flashbase; -void check_chip_supported(struct flashchip *flash); +void check_chip_supported(const struct flashchip *flash); int check_max_decode(enum chipbustype buses, uint32_t size); char *extract_programmer_param(char *param_name);

1 0

[PATCH] Revert MMIO space writes on shutdown as needed.
by Carl-Daniel Hailfinger 03 May '11

03 May '11

Revert MMIO space writes on shutdown as needed. Reversible MMIO space writes now use rmmio_write*(). MMIO space writes which are one-shot (e.g. communication with some chip) should continue to use the permanent mmio_write* variants. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-mmio_shutdown_restore/hwaccess.c =================================================================== --- flashrom-mmio_shutdown_restore/hwaccess.c (Revision 1234) +++ flashrom-mmio_shutdown_restore/hwaccess.c (Arbeitskopie) @@ -184,3 +184,71 @@ { return le_to_cpu32(mmio_readl(addr)); } + +enum mmio_write_type { + mmio_write_type_b, + mmio_write_type_w, + mmio_write_type_l, +}; + +struct undo_mmio_write_data { + void *addr; + int reg; + enum mmio_write_type type; + union { + uint8_t bdata; + uint16_t wdata; + uint32_t ldata; + }; +}; + +void undo_mmio_write(void *p) +{ + struct undo_mmio_write_data *data = p; + msg_pdbg("Restoring MMIO space at %p\n", data->addr); + switch (data->type) { + case mmio_write_type_b: + mmio_writeb(data->bdata, data->addr); + break; + case mmio_write_type_w: + mmio_writeb(data->wdata, data->addr); + break; + case mmio_write_type_l: + mmio_writeb(data->ldata, data->addr); + break; + } + /* p was allocated in register_undo_mmio_write. */ + free(p); +} + +#define register_undo_mmio_write(a, c) \ +{ \ + struct undo_mmio_write_data *undo_mmio_write_data; \ + undo_mmio_write_data = malloc(sizeof(struct undo_mmio_write_data)); \ + undo_mmio_write_data->addr = a; \ + undo_mmio_write_data->type = mmio_write_type_##c; \ + undo_mmio_write_data->c##data = mmio_read##c(a); \ + register_shutdown(undo_mmio_write, undo_mmio_write_data); \ +} + +#define register_undo_mmio_writeb(a) register_undo_mmio_write(a, b) +#define register_undo_mmio_writew(a) register_undo_mmio_write(a, w) +#define register_undo_mmio_writel(a) register_undo_mmio_write(a, l) + +void rmmio_writeb(uint8_t val, void *addr) +{ + register_undo_mmio_writeb(addr); + mmio_writeb(val, addr); +} + +void rmmio_writew(uint16_t val, void *addr) +{ + register_undo_mmio_writew(addr); + mmio_writew(val, addr); +} + +void rmmio_writel(uint32_t val, void *addr) +{ + register_undo_mmio_writel(addr); + mmio_writel(val, addr); +} Index: flashrom-mmio_shutdown_restore/ichspi.c =================================================================== --- flashrom-mmio_shutdown_restore/ichspi.c (Revision 1234) +++ flashrom-mmio_shutdown_restore/ichspi.c (Arbeitskopie) @@ -382,16 +382,16 @@ switch (spi_controller) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: - REGWRITE16(ICH7_REG_PREOP, preop); - REGWRITE16(ICH7_REG_OPTYPE, optype); - REGWRITE32(ICH7_REG_OPMENU, opmenu[0]); - REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]); + rmmio_writew(preop, ich_spibar + ICH7_REG_PREOP); + rmmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE); + rmmio_writew(opmenu[0], ich_spibar + ICH7_REG_OPMENU); + rmmio_writew(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); break; case SPI_CONTROLLER_ICH9: - REGWRITE16(ICH9_REG_PREOP, preop); - REGWRITE16(ICH9_REG_OPTYPE, optype); - REGWRITE32(ICH9_REG_OPMENU, opmenu[0]); - REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]); + rmmio_writew(preop, ich_spibar + ICH9_REG_PREOP); + rmmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE); + rmmio_writew(opmenu[0], ich_spibar + ICH9_REG_OPMENU); + rmmio_writew(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); break; default: msg_perr("%s: unsupported chipset\n", __func__); @@ -409,16 +409,20 @@ { switch (spi_controller) { case SPI_CONTROLLER_ICH7: - mmio_writel(minaddr, ich_spibar + 0x50); + rmmio_writel(minaddr, ich_spibar + 0x50); ichspi_bbar = mmio_readl(ich_spibar + 0x50); - /* We don't have any option except complaining. */ + /* We don't have any option except complaining. And if the write + * failed, the restore will fail as well, so no problem there. + */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); break; case SPI_CONTROLLER_ICH9: - mmio_writel(minaddr, ich_spibar + 0xA0); + rmmio_writel(minaddr, ich_spibar + 0xA0); ichspi_bbar = mmio_readl(ich_spibar + 0xA0); - /* We don't have any option except complaining. */ + /* We don't have any option except complaining. And if the write + * failed, the restore will fail as well, so no problem there. + */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); break; Index: flashrom-mmio_shutdown_restore/nicintel_spi.c =================================================================== --- flashrom-mmio_shutdown_restore/nicintel_spi.c (Revision 1234) +++ flashrom-mmio_shutdown_restore/nicintel_spi.c (Arbeitskopie) @@ -149,6 +149,7 @@ nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, 4096); + /* Automatic restore is not possible because we only change two bits. */ tmp = pci_mmio_readl(nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_DISABLED; tmp |= FLASH_WRITES_ENABLED; @@ -168,6 +169,7 @@ { uint32_t tmp; + /* Automatic restore is not possible because we only change two bits. */ tmp = pci_mmio_readl(nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_ENABLED; tmp |= FLASH_WRITES_DISABLED; Index: flashrom-mmio_shutdown_restore/programmer.h =================================================================== --- flashrom-mmio_shutdown_restore/programmer.h (Revision 1234) +++ flashrom-mmio_shutdown_restore/programmer.h (Arbeitskopie) @@ -311,6 +311,9 @@ #define pci_mmio_readb mmio_le_readb #define pci_mmio_readw mmio_le_readw #define pci_mmio_readl mmio_le_readl +void rmmio_writeb(uint8_t val, void *addr); +void rmmio_writew(uint16_t val, void *addr); +void rmmio_writel(uint32_t val, void *addr); /* programmer.c */ int noop_shutdown(void); -- http://www.hailfinger.org/

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flashrom May 2011