Remove the array spi_programmer, replace it by dynamic registration
instead. Also initially start with no busses supported, and switch to
the default non-SPI only for the internal programmer.
Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de>
---
bitbang_spi.c | 14 ++++-
buspirate_spi.c | 15 +++-
dediprog.c | 19 ++++--
dummyflasher.c | 17 ++++-
flashrom.c | 9 +--
ft2232_spi.c | 15 +++-
ichspi.c | 57 ++++++++++++----
internal.c | 5 ++
it85spi.c | 18 ++++--
it87spi.c | 19 ++++--
mcp6x_spi.c | 3 -
nicintel_spi.c | 3 -
ogp_spi.c | 3 -
programmer.h | 40 ++----------
rayer_spi.c | 3 -
sb600spi.c | 15 +++-
spi.c | 204 +++++++------------------------------------------------
spi25.c | 4 +-
wbsio_spi.c | 17 ++++-
19 files changed, 198 insertions(+), 282 deletions(-)
diff --git a/bitbang_spi.c b/bitbang_spi.c
index be30944..ca28434 100644
--- a/bitbang_spi.c
+++ b/bitbang_spi.c
@@ -81,7 +81,7 @@ static uint8_t bitbang_spi_readwrite_byte(uint8_t val)
return ret;
}
-int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt,
+static int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr)
{
int i;
@@ -106,6 +106,16 @@ int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt,
return 0;
}
+static const struct spi_programmer spi_programmer_bitbang = {
+ .type = SPI_CONTROLLER_BITBANG,
+ .max_data_read = MAX_DATA_READ_UNLIMITED,
+ .max_data_write = MAX_DATA_WRITE_UNLIMITED,
+ .command = bitbang_spi_send_command,
+ .multicommand = default_spi_send_multicommand,
+ .read = default_spi_read,
+ .write_256 = default_spi_write_256,
+};
+
int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod)
{
/* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type,
@@ -127,6 +137,8 @@ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod)
bitbang_spi_master = master;
bitbang_spi_half_period = halfperiod;
+ register_spi_programmer(&spi_programmer_bitbang);
+
/* FIXME: Run bitbang_spi_request_bus here or in programmer init? */
bitbang_spi_set_cs(1);
bitbang_spi_set_sck(0);
diff --git a/buspirate_spi.c b/buspirate_spi.c
index 89f529d..57d5ce2 100644
--- a/buspirate_spi.c
+++ b/buspirate_spi.c
@@ -116,7 +116,7 @@ int buspirate_spi_shutdown(void)
return 0;
}
-int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt,
+static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr)
{
static unsigned char *buf = NULL;
@@ -172,6 +172,16 @@ int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt,
return ret;
}
+static const struct spi_programmer spi_programmer_buspirate = {
+ .type = SPI_CONTROLLER_BUSPIRATE,
+ .max_data_read = 12,
+ .max_data_write = 12,
+ .command = buspirate_spi_send_command,
+ .multicommand = default_spi_send_multicommand,
+ .read = default_spi_read,
+ .write_256 = default_spi_write_256,
+};
+
static const struct buspirate_spispeeds spispeeds[] = {
{"30k", 0x0},
{"125k", 0x1},
@@ -321,8 +331,7 @@ int buspirate_spi_init(void)
return 1;
}
- buses_supported = CHIP_BUSTYPE_SPI;
- spi_controller = SPI_CONTROLLER_BUSPIRATE;
+ register_spi_programmer(&spi_programmer_buspirate);
return 0;
}
diff --git a/dediprog.c b/dediprog.c
index 989306a..1c54c66 100644
--- a/dediprog.c
+++ b/dediprog.c
@@ -248,7 +248,7 @@ static int dediprog_spi_bulk_read(struct flashchip *flash, uint8_t *buf,
return 0;
}
-int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len)
+static int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len)
{
int ret;
/* chunksize must be 512, other sizes will NOT work at all. */
@@ -293,7 +293,7 @@ int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len)
return 0;
}
-int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len)
+static int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len)
{
int ret;
@@ -310,7 +310,7 @@ int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int
return ret;
}
-int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt,
+static int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr)
{
int ret;
@@ -526,6 +526,16 @@ static int parse_voltage(char *voltage)
return millivolt;
}
+static const struct spi_programmer spi_programmer_dediprog = {
+ .type = SPI_CONTROLLER_DEDIPROG,
+ .max_data_read = MAX_DATA_UNSPECIFIED,
+ .max_data_write = MAX_DATA_UNSPECIFIED,
+ .command = dediprog_spi_send_command,
+ .multicommand = default_spi_send_multicommand,
+ .read = dediprog_spi_read,
+ .write_256 = dediprog_spi_write_256,
+};
+
/* URB numbers refer to the first log ever captured. */
int dediprog_init(void)
{
@@ -606,8 +616,7 @@ int dediprog_init(void)
return 1;
}
- buses_supported = CHIP_BUSTYPE_SPI;
- spi_controller = SPI_CONTROLLER_DEDIPROG;
+ register_spi_programmer(&spi_programmer_dediprog);
/* RE leftover, leave in until the driver is complete. */
#if 0
diff --git a/dummyflasher.c b/dummyflasher.c
index c4c9c4e..fdaa5f2 100644
--- a/dummyflasher.c
+++ b/dummyflasher.c
@@ -339,7 +339,7 @@ static int emulate_spi_chip_response(unsigned int writecnt, unsigned int readcnt
}
#endif
-int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt,
+static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr)
{
int i;
@@ -375,12 +375,22 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt,
return 0;
}
-int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len)
+static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len)
{
return spi_write_chunked(flash, buf, start, len,
spi_write_256_chunksize);
}
+static const struct spi_programmer spi_programmer_dummyflasher = {
+ .type = SPI_CONTROLLER_DUMMY,
+ .max_data_read = MAX_DATA_READ_UNLIMITED,
+ .max_data_write = MAX_DATA_UNSPECIFIED,
+ .command = dummy_spi_send_command,
+ .multicommand = default_spi_send_multicommand,
+ .read = default_spi_read,
+ .write_256 = dummy_spi_write_256,
+};
+
int dummy_init(void)
{
char *bustext = NULL;
@@ -412,8 +422,7 @@ int dummy_init(void)
msg_pdbg("Enabling support for %s flash.\n", "FWH");
}
if (strstr(bustext, "spi")) {
- buses_supported |= CHIP_BUSTYPE_SPI;
- spi_controller = SPI_CONTROLLER_DUMMY;
+ register_spi_programmer(&spi_programmer_dummyflasher);
msg_pdbg("Enabling support for %s flash.\n", "SPI");
}
if (buses_supported == CHIP_BUSTYPE_NONE)
diff --git a/flashrom.c b/flashrom.c
index 1083abe..dc9e1d1 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -499,10 +499,7 @@ int programmer_init(char *param)
.fwh = 0xffffffff,
.spi = 0xffffffff
};
- /* Default to Parallel/LPC/FWH flash devices. If a known host controller
- * is found, the init routine sets the buses_supported bitfield.
- */
- buses_supported = CHIP_BUSTYPE_NONSPI;
+ buses_supported = CHIP_BUSTYPE_NONE;
/* Default to top aligned flash at 4 GB. */
flashbase = 0;
/* Registering shutdown functions is now allowed. */
@@ -1690,10 +1687,6 @@ int selfcheck(void)
msg_gerr("Programmer table miscompilation!\n");
ret = 1;
}
- if (spi_programmer_count - 1 != SPI_CONTROLLER_INVALID) {
- msg_gerr("SPI programmer table miscompilation!\n");
- ret = 1;
- }
for (flash = flashchips; flash && flash->name; flash++)
if (selfcheck_eraseblocks(flash))
ret = 1;
diff --git a/ft2232_spi.c b/ft2232_spi.c
index 4e0fc67..c114e41 100644
--- a/ft2232_spi.c
+++ b/ft2232_spi.c
@@ -128,7 +128,7 @@ static int get_buf(struct ftdi_context *ftdic, const unsigned char *buf,
return 0;
}
-int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt,
+static int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr)
{
struct ftdi_context *ftdic = &ftdic_context;
@@ -213,6 +213,16 @@ int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt,
return failed ? -1 : 0;
}
+static const struct spi_programmer spi_programmer_ft2232 = {
+ .type = SPI_CONTROLLER_FT2232,
+ .max_data_read = 64 * 1024,
+ .max_data_write = 256,
+ .command = ft2232_spi_send_command,
+ .multicommand = default_spi_send_multicommand,
+ .read = default_spi_read,
+ .write_256 = default_spi_write_256,
+};
+
int ft2232_spi_init(void)
{
int f;
@@ -346,8 +356,7 @@ int ft2232_spi_init(void)
// msg_pdbg("\nft2232 chosen\n");
- buses_supported = CHIP_BUSTYPE_SPI;
- spi_controller = SPI_CONTROLLER_FT2232;
+ register_spi_programmer(&spi_programmer_ft2232);
return 0;
}
diff --git a/ichspi.c b/ichspi.c
index 4315e78..ddd14d3 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -313,7 +313,7 @@ static int generate_opcodes(OPCODES * op)
return -1;
}
- switch (spi_controller) {
+ switch (spi_programmer->type) {
case SPI_CONTROLLER_ICH7:
case SPI_CONTROLLER_VIA:
preop = REGREAD16(ICH7_REG_PREOP);
@@ -388,7 +388,7 @@ static int program_opcodes(OPCODES *op, int enable_undo)
}
msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
- switch (spi_controller) {
+ switch (spi_programmer->type) {
case SPI_CONTROLLER_ICH7:
case SPI_CONTROLLER_VIA:
/* Register undo only for enable_undo=1, i.e. first call. */
@@ -432,7 +432,7 @@ void ich_set_bbar(uint32_t minaddr)
{
#define BBAR_MASK 0x00ffff00
minaddr &= BBAR_MASK;
- switch (spi_controller) {
+ switch (spi_programmer->type) {
case SPI_CONTROLLER_ICH7:
case SPI_CONTROLLER_VIA:
ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK;
@@ -801,7 +801,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
static int run_opcode(OPCODE op, uint32_t offset,
uint8_t datalength, uint8_t * data)
{
- switch (spi_controller) {
+ switch (spi_programmer->type) {
case SPI_CONTROLLER_VIA:
if (datalength > 16) {
msg_perr("%s: Internal command size error for "
@@ -834,7 +834,7 @@ static int run_opcode(OPCODE op, uint32_t offset,
return -1;
}
-int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
+static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr)
{
int result;
@@ -900,7 +900,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
addr = (writearr[1] << 16) |
(writearr[2] << 8) | (writearr[3] << 0);
- switch (spi_controller) {
+ switch (spi_programmer->type) {
case SPI_CONTROLLER_ICH7:
case SPI_CONTROLLER_VIA:
case SPI_CONTROLLER_ICH9:
@@ -953,7 +953,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
return result;
}
-int ich_spi_send_multicommand(struct spi_command *cmds)
+static int ich_spi_send_multicommand(struct spi_command *cmds)
{
int ret = 0;
int i;
@@ -1051,6 +1051,26 @@ static void do_ich9_spi_frap(uint32_t frap, int i)
access_names[rwperms]);
}
+static const struct spi_programmer spi_programmer_ich7 = {
+ .type = SPI_CONTROLLER_ICH7,
+ .max_data_read = 64,
+ .max_data_write = 64,
+ .command = ich_spi_send_command,
+ .multicommand = ich_spi_send_multicommand,
+ .read = default_spi_read,
+ .write_256 = default_spi_write_256,
+};
+
+static const struct spi_programmer spi_programmer_ich9 = {
+ .type = SPI_CONTROLLER_ICH9,
+ .max_data_read = 64,
+ .max_data_write = 64,
+ .command = ich_spi_send_command,
+ .multicommand = ich_spi_send_multicommand,
+ .read = default_spi_read,
+ .write_256 = default_spi_write_256,
+};
+
int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
int ich_generation)
{
@@ -1059,20 +1079,19 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
uint16_t spibar_offset, tmp2;
uint32_t tmp;
- buses_supported |= CHIP_BUSTYPE_SPI;
switch (ich_generation) {
case 7:
- spi_controller = SPI_CONTROLLER_ICH7;
+ register_spi_programmer(&spi_programmer_ich7);
spibar_offset = 0x3020;
break;
case 8:
- spi_controller = SPI_CONTROLLER_ICH9;
+ register_spi_programmer(&spi_programmer_ich9);
spibar_offset = 0x3020;
break;
case 9:
case 10:
default: /* Future version might behave the same */
- spi_controller = SPI_CONTROLLER_ICH9;
+ register_spi_programmer(&spi_programmer_ich9);
spibar_offset = 0x3800;
break;
}
@@ -1083,7 +1102,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
/* Assign Virtual Address */
ich_spibar = rcrb + spibar_offset;
- switch (spi_controller) {
+ switch (spi_programmer->type) {
case SPI_CONTROLLER_ICH7:
msg_pdbg("0x00: 0x%04x (SPIS)\n",
mmio_readw(ich_spibar + 0));
@@ -1211,6 +1230,16 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
return 0;
}
+static const struct spi_programmer spi_programmer_via = {
+ .type = SPI_CONTROLLER_VIA,
+ .max_data_read = 16,
+ .max_data_write = 16,
+ .command = ich_spi_send_command,
+ .multicommand = ich_spi_send_multicommand,
+ .read = default_spi_read,
+ .write_256 = default_spi_write_256,
+};
+
int via_init_spi(struct pci_dev *dev)
{
uint32_t mmio_base;
@@ -1221,8 +1250,8 @@ int via_init_spi(struct pci_dev *dev)
ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
/* Not sure if it speaks all these bus protocols. */
- buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
- spi_controller = SPI_CONTROLLER_VIA;
+ buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
+ register_spi_programmer(&spi_programmer_via);
msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
diff --git a/internal.c b/internal.c
index d3866ba..9639460 100644
--- a/internal.c
+++ b/internal.c
@@ -178,6 +178,11 @@ int internal_init(void)
get_io_perms();
+ /* Default to Parallel/LPC/FWH flash devices. If a known host controller
+ * is found, the init routine sets the buses_supported bitfield.
+ */
+ buses_supported = CHIP_BUSTYPE_NONSPI;
+
/* Initialize PCI access for flash enables */
pacc = pci_alloc(); /* Get the pci_access structure */
/* Set all options you want -- here we stick with the defaults */
diff --git a/it85spi.c b/it85spi.c
index 11a2ff5..acd84ab 100644
--- a/it85spi.c
+++ b/it85spi.c
@@ -233,7 +233,7 @@ void it85xx_exit_scratch_rom()
* 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get
* data from MISO)
*/
-int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,
+static int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr)
{
int i;
@@ -313,12 +313,19 @@ static int it85xx_spi_common_init(struct superio s)
ce_low = (unsigned char*)(base + 0xD00); /* 0xFFFFFD00 */
#endif
- /* Set this as spi controller. */
- spi_controller = SPI_CONTROLLER_IT85XX;
-
return 0;
}
+static const struct spi_programmer spi_programmer_it85xx = {
+ .type = SPI_CONTROLLER_IT85XX,
+ .max_data_read = 64,
+ .max_data_write = 64,
+ .command = it85xx_spi_send_command,
+ .multicommand = default_spi_send_multicommand,
+ .read = default_spi_read,
+ .write_256 = default_spi_write_256,
+};
+
int it85xx_spi_init(struct superio s)
{
int ret;
@@ -335,7 +342,8 @@ int it85xx_spi_init(struct superio s)
if (buses_supported & CHIP_BUSTYPE_FWH)
msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n");
/* Really leave FWH enabled? */
- buses_supported |= CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
+ /* Set this as spi controller. */
+ register_spi_programmer(&spi_programmer_it85xx);
}
return ret;
}
diff --git a/it87spi.c b/it87spi.c
index fdf6ccb..fadf5a1 100644
--- a/it87spi.c
+++ b/it87spi.c
@@ -113,7 +113,7 @@ void probe_superio_ite(void)
* commands with the address in inverse wire order. That's why the register
* ordering in case 4 and 5 may seem strange.
*/
-int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt,
+static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr)
{
uint8_t busy, writeenc;
@@ -206,7 +206,7 @@ static int it8716f_spi_page_program(struct flashchip *flash, uint8_t *buf, int s
* IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
* Need to read this big flash using firmware cycles 3 byte at a time.
*/
-int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
+static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
{
fast_spi = 0;
@@ -223,7 +223,7 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int
return 0;
}
-int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len)
+static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len)
{
/*
* IT8716F only allows maximum of 512 kb SPI chip size for memory
@@ -265,6 +265,16 @@ int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start,
return 0;
}
+static const struct spi_programmer spi_programmer_it87xx = {
+ .type = SPI_CONTROLLER_IT87XX,
+ .max_data_read = MAX_DATA_UNSPECIFIED,
+ .max_data_write = MAX_DATA_UNSPECIFIED,
+ .command = it8716f_spi_send_command,
+ .multicommand = default_spi_send_multicommand,
+ .read = it8716f_spi_chip_read,
+ .write_256 = it8716f_spi_chip_write_256,
+};
+
static uint16_t it87spi_probe(uint16_t port)
{
uint8_t tmp = 0;
@@ -341,9 +351,8 @@ static uint16_t it87spi_probe(uint16_t port)
it8716f_flashport = flashport;
if (buses_supported & CHIP_BUSTYPE_SPI)
msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
- spi_controller = SPI_CONTROLLER_IT87XX;
/* FIXME: Add the SPI bus or replace the other buses with it? */
- buses_supported |= CHIP_BUSTYPE_SPI;
+ register_spi_programmer(&spi_programmer_it87xx);
return 0;
}
diff --git a/mcp6x_spi.c b/mcp6x_spi.c
index 0e0d311..d2c31be 100644
--- a/mcp6x_spi.c
+++ b/mcp6x_spi.c
@@ -166,9 +166,6 @@ int mcp6x_spi_init(int want_spi)
return 1;
}
- buses_supported |= CHIP_BUSTYPE_SPI;
- spi_controller = SPI_CONTROLLER_MCP6X_BITBANG;
-
return 0;
}
diff --git a/nicintel_spi.c b/nicintel_spi.c
index 28d332e..ee7046c 100644
--- a/nicintel_spi.c
+++ b/nicintel_spi.c
@@ -162,9 +162,6 @@ int nicintel_spi_init(void)
if (bitbang_spi_init(&bitbang_spi_master_nicintel, 1))
return 1;
- buses_supported = CHIP_BUSTYPE_SPI;
- spi_controller = SPI_CONTROLLER_NICINTEL;
-
return 0;
}
diff --git a/ogp_spi.c b/ogp_spi.c
index 6932f06..2916ae1 100644
--- a/ogp_spi.c
+++ b/ogp_spi.c
@@ -128,9 +128,6 @@ int ogp_spi_init(void)
if (bitbang_spi_init(&bitbang_spi_master_ogp, 0))
return 1;
- buses_supported = CHIP_BUSTYPE_SPI;
- spi_controller = SPI_CONTROLLER_OGP;
-
return 0;
}
diff --git a/programmer.h b/programmer.h
index fefb9cd..53a50f6 100644
--- a/programmer.h
+++ b/programmer.h
@@ -356,9 +356,6 @@ uint8_t dummy_chip_readb(const chipaddr addr);
uint16_t dummy_chip_readw(const chipaddr addr);
uint32_t dummy_chip_readl(const chipaddr addr);
void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
-int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt,
- const unsigned char *writearr, unsigned char *readarr);
-int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
#endif
/* nic3com.c */
@@ -460,7 +457,6 @@ struct usbdev_status {
const char *device_name;
};
int ft2232_spi_init(void);
-int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
extern const struct usbdev_status devs_ft2232spi[];
void print_supported_usbdevs(const struct usbdev_status *devs);
#endif
@@ -480,7 +476,6 @@ int mcp6x_spi_init(int want_spi);
/* bitbang_spi.c */
int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod);
int bitbang_spi_shutdown(const struct bitbang_spi_master *master);
-int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
/* buspirate_spi.c */
struct buspirate_spispeeds {
@@ -489,14 +484,10 @@ struct buspirate_spispeeds {
};
int buspirate_spi_init(void);
int buspirate_spi_shutdown(void);
-int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
/* dediprog.c */
int dediprog_init(void);
int dediprog_shutdown(void);
-int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
-int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
-int dediprog_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
/* flashrom.c */
struct decode_sizes {
@@ -527,7 +518,6 @@ enum spi_controller {
SPI_CONTROLLER_SB600,
SPI_CONTROLLER_VIA,
SPI_CONTROLLER_WBSIO,
- SPI_CONTROLLER_MCP6X_BITBANG,
#endif
#endif
#if CONFIG_FT2232_SPI == 1
@@ -542,16 +532,9 @@ enum spi_controller {
#if CONFIG_DEDIPROG == 1
SPI_CONTROLLER_DEDIPROG,
#endif
-#if CONFIG_RAYER_SPI == 1
- SPI_CONTROLLER_RAYER,
-#endif
-#if CONFIG_NICINTEL_SPI == 1
- SPI_CONTROLLER_NICINTEL,
-#endif
-#if CONFIG_OGP_SPI == 1
- SPI_CONTROLLER_OGP,
+#if CONFIG_OGP_SPI == 1 || CONFIG_NICINTEL_SPI == 1 || CONFIG_RAYER_SPI == 1 || (CONFIG_INTERNAL == 1 && (defined(__i386__) || defined(__x86_64__)))
+ SPI_CONTROLLER_BITBANG,
#endif
- SPI_CONTROLLER_INVALID /* This must always be the last entry. */
};
extern const int spi_programmer_count;
@@ -559,6 +542,7 @@ extern const int spi_programmer_count;
#define MAX_DATA_READ_UNLIMITED 64 * 1024
#define MAX_DATA_WRITE_UNLIMITED 256
struct spi_programmer {
+ enum spi_controller type;
int max_data_read;
int max_data_write;
int (*command)(unsigned int writecnt, unsigned int readcnt,
@@ -570,13 +554,13 @@ struct spi_programmer {
int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len);
};
-extern enum spi_controller spi_controller;
-extern const struct spi_programmer spi_programmer[];
+extern const struct spi_programmer *spi_programmer;
int default_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr);
int default_spi_send_multicommand(struct spi_command *cmds);
int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
+void register_spi_programmer(const struct spi_programmer *programmer);
/* ichspi.c */
#if CONFIG_INTERNAL == 1
@@ -584,40 +568,26 @@ extern uint32_t ichspi_bbar;
int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
int ich_generation);
int via_init_spi(struct pci_dev *dev);
-int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
- const unsigned char *writearr, unsigned char *readarr);
-int ich_spi_send_multicommand(struct spi_command *cmds);
#endif
/* it85spi.c */
int it85xx_spi_init(struct superio s);
int it85xx_shutdown(void);
-int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,
- const unsigned char *writearr, unsigned char *readarr);
/* it87spi.c */
void enter_conf_mode_ite(uint16_t port);
void exit_conf_mode_ite(uint16_t port);
void probe_superio_ite(void);
int init_superio_ite(void);
-int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt,
- const unsigned char *writearr, unsigned char *readarr);
-int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len);
-int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
/* sb600spi.c */
#if CONFIG_INTERNAL == 1
int sb600_probe_spi(struct pci_dev *dev);
-int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt,
- const unsigned char *writearr, unsigned char *readarr);
#endif
/* wbsio_spi.c */
#if CONFIG_INTERNAL == 1
int wbsio_check_for_spi(void);
-int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt,
- const unsigned char *writearr, unsigned char *readarr);
-int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
#endif
/* serprog.c */
diff --git a/rayer_spi.c b/rayer_spi.c
index a01ee80..0807487 100644
--- a/rayer_spi.c
+++ b/rayer_spi.c
@@ -134,9 +134,6 @@ int rayer_spi_init(void)
if (bitbang_spi_init(&bitbang_spi_master_rayer, 0))
return 1;
- buses_supported = CHIP_BUSTYPE_SPI;
- spi_controller = SPI_CONTROLLER_RAYER;
-
return 0;
}
diff --git a/sb600spi.c b/sb600spi.c
index 269af8a..37aac3b 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -89,7 +89,7 @@ static void execute_command(void)
;
}
-int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt,
+static int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr)
{
int count;
@@ -192,6 +192,16 @@ int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt,
return 0;
}
+static const struct spi_programmer spi_programmer_sb600 = {
+ .type = SPI_CONTROLLER_SB600,
+ .max_data_read = 8,
+ .max_data_write = 5,
+ .command = sb600_spi_send_command,
+ .multicommand = default_spi_send_multicommand,
+ .read = default_spi_read,
+ .write_256 = default_spi_write_256,
+};
+
int sb600_probe_spi(struct pci_dev *dev)
{
struct pci_dev *smbus_dev;
@@ -304,8 +314,7 @@ int sb600_probe_spi(struct pci_dev *dev)
/* Bring the FIFO to a clean state. */
reset_internal_fifo_pointer();
- buses_supported |= CHIP_BUSTYPE_SPI;
- spi_controller = SPI_CONTROLLER_SB600;
+ register_spi_programmer(&spi_programmer_sb600);
return 0;
}
diff --git a/spi.c b/spi.c
index 5857fda..4610102 100644
--- a/spi.c
+++ b/spi.c
@@ -30,200 +30,42 @@
#include "programmer.h"
#include "spi.h"
-enum spi_controller spi_controller = SPI_CONTROLLER_NONE;
-
-const struct spi_programmer spi_programmer[] = {
- { /* SPI_CONTROLLER_NONE */
- .max_data_read = MAX_DATA_UNSPECIFIED,
- .max_data_write = MAX_DATA_UNSPECIFIED,
- .command = NULL,
- .multicommand = NULL,
- .read = NULL,
- .write_256 = NULL,
- },
-
-#if CONFIG_INTERNAL == 1
-#if defined(__i386__) || defined(__x86_64__)
- { /* SPI_CONTROLLER_ICH7 */
- .max_data_read = 64,
- .max_data_write = 64,
- .command = ich_spi_send_command,
- .multicommand = ich_spi_send_multicommand,
- .read = default_spi_read,
- .write_256 = default_spi_write_256,
- },
-
- { /* SPI_CONTROLLER_ICH9 */
- .max_data_read = 64,
- .max_data_write = 64,
- .command = ich_spi_send_command,
- .multicommand = ich_spi_send_multicommand,
- .read = default_spi_read,
- .write_256 = default_spi_write_256,
- },
-
- { /* SPI_CONTROLLER_IT85XX */
- .max_data_read = 64,
- .max_data_write = 64,
- .command = it85xx_spi_send_command,
- .multicommand = default_spi_send_multicommand,
- .read = default_spi_read,
- .write_256 = default_spi_write_256,
- },
-
- { /* SPI_CONTROLLER_IT87XX */
- .max_data_read = MAX_DATA_UNSPECIFIED,
- .max_data_write = MAX_DATA_UNSPECIFIED,
- .command = it8716f_spi_send_command,
- .multicommand = default_spi_send_multicommand,
- .read = it8716f_spi_chip_read,
- .write_256 = it8716f_spi_chip_write_256,
- },
-
- { /* SPI_CONTROLLER_SB600 */
- .max_data_read = 8,
- .max_data_write = 5,
- .command = sb600_spi_send_command,
- .multicommand = default_spi_send_multicommand,
- .read = default_spi_read,
- .write_256 = default_spi_write_256,
- },
-
- { /* SPI_CONTROLLER_VIA */
- .max_data_read = 16,
- .max_data_write = 16,
- .command = ich_spi_send_command,
- .multicommand = ich_spi_send_multicommand,
- .read = default_spi_read,
- .write_256 = default_spi_write_256,
- },
-
- { /* SPI_CONTROLLER_WBSIO */
- .max_data_read = MAX_DATA_UNSPECIFIED,
- .max_data_write = MAX_DATA_UNSPECIFIED,
- .command = wbsio_spi_send_command,
- .multicommand = default_spi_send_multicommand,
- .read = wbsio_spi_read,
- .write_256 = spi_chip_write_1,
- },
-
- { /* SPI_CONTROLLER_MCP6X_BITBANG */
- .max_data_read = MAX_DATA_READ_UNLIMITED,
- .max_data_write = MAX_DATA_WRITE_UNLIMITED,
- .command = bitbang_spi_send_command,
- .multicommand = default_spi_send_multicommand,
- .read = default_spi_read,
- .write_256 = default_spi_write_256,
- },
-#endif
-#endif
-
-#if CONFIG_FT2232_SPI == 1
- { /* SPI_CONTROLLER_FT2232 */
- .max_data_read = 64 * 1024,
- .max_data_write = 256,
- .command = ft2232_spi_send_command,
- .multicommand = default_spi_send_multicommand,
- .read = default_spi_read,
- .write_256 = default_spi_write_256,
- },
-#endif
-
-#if CONFIG_DUMMY == 1
- { /* SPI_CONTROLLER_DUMMY */
- .max_data_read = MAX_DATA_READ_UNLIMITED,
- .max_data_write = MAX_DATA_UNSPECIFIED,
- .command = dummy_spi_send_command,
- .multicommand = default_spi_send_multicommand,
- .read = default_spi_read,
- .write_256 = dummy_spi_write_256,
- },
-#endif
-
-#if CONFIG_BUSPIRATE_SPI == 1
- { /* SPI_CONTROLLER_BUSPIRATE */
- .max_data_read = 12,
- .max_data_write = 12,
- .command = buspirate_spi_send_command,
- .multicommand = default_spi_send_multicommand,
- .read = default_spi_read,
- .write_256 = default_spi_write_256,
- },
-#endif
-
-#if CONFIG_DEDIPROG == 1
- { /* SPI_CONTROLLER_DEDIPROG */
- .max_data_read = MAX_DATA_UNSPECIFIED,
- .max_data_write = MAX_DATA_UNSPECIFIED,
- .command = dediprog_spi_send_command,
- .multicommand = default_spi_send_multicommand,
- .read = dediprog_spi_read,
- .write_256 = dediprog_spi_write_256,
- },
-#endif
-
-#if CONFIG_RAYER_SPI == 1
- { /* SPI_CONTROLLER_RAYER */
- .max_data_read = MAX_DATA_READ_UNLIMITED,
- .max_data_write = MAX_DATA_WRITE_UNLIMITED,
- .command = bitbang_spi_send_command,
- .multicommand = default_spi_send_multicommand,
- .read = default_spi_read,
- .write_256 = default_spi_write_256,
- },
-#endif
-
-#if CONFIG_NICINTEL_SPI == 1
- { /* SPI_CONTROLLER_NICINTEL */
- .max_data_read = MAX_DATA_READ_UNLIMITED,
- .max_data_write = MAX_DATA_WRITE_UNLIMITED,
- .command = bitbang_spi_send_command,
- .multicommand = default_spi_send_multicommand,
- .read = default_spi_read,
- .write_256 = default_spi_write_256,
- },
-#endif
-
-#if CONFIG_OGP_SPI == 1
- { /* SPI_CONTROLLER_OGP */
- .max_data_read = MAX_DATA_READ_UNLIMITED,
- .max_data_write = MAX_DATA_WRITE_UNLIMITED,
- .command = bitbang_spi_send_command,
- .multicommand = default_spi_send_multicommand,
- .read = default_spi_read,
- .write_256 = default_spi_write_256,
- },
-#endif
-
- {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */
+const struct spi_programmer spi_programmer_none = {
+ .type = SPI_CONTROLLER_NONE,
+ .max_data_read = MAX_DATA_UNSPECIFIED,
+ .max_data_write = MAX_DATA_UNSPECIFIED,
+ .command = NULL,
+ .multicommand = NULL,
+ .read = NULL,
+ .write_256 = NULL,
};
-const int spi_programmer_count = ARRAY_SIZE(spi_programmer);
+const struct spi_programmer *spi_programmer = &spi_programmer_none;
int spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr)
{
- if (!spi_programmer[spi_controller].command) {
+ if (!spi_programmer->command) {
msg_perr("%s called, but SPI is unsupported on this "
"hardware. Please report a bug at "
"flashrom(a)flashrom.org\n", __func__);
return 1;
}
- return spi_programmer[spi_controller].command(writecnt, readcnt,
+ return spi_programmer->command(writecnt, readcnt,
writearr, readarr);
}
int spi_send_multicommand(struct spi_command *cmds)
{
- if (!spi_programmer[spi_controller].multicommand) {
+ if (!spi_programmer->multicommand) {
msg_perr("%s called, but SPI is unsupported on this "
"hardware. Please report a bug at "
"flashrom(a)flashrom.org\n", __func__);
return 1;
}
- return spi_programmer[spi_controller].multicommand(cmds);
+ return spi_programmer->multicommand(cmds);
}
int default_spi_send_command(unsigned int writecnt, unsigned int readcnt,
@@ -257,7 +99,7 @@ int default_spi_send_multicommand(struct spi_command *cmds)
int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len)
{
- int max_data = spi_programmer[spi_controller].max_data_read;
+ int max_data = spi_programmer->max_data_read;
if (max_data == MAX_DATA_UNSPECIFIED) {
msg_perr("%s called, but SPI read chunk size not defined "
"on this hardware. Please report a bug at "
@@ -269,7 +111,7 @@ int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len)
int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len)
{
- int max_data = spi_programmer[spi_controller].max_data_write;
+ int max_data = spi_programmer->max_data_write;
if (max_data == MAX_DATA_UNSPECIFIED) {
msg_perr("%s called, but SPI write chunk size not defined "
"on this hardware. Please report a bug at "
@@ -282,7 +124,7 @@ int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int
int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
{
int addrbase = 0;
- if (!spi_programmer[spi_controller].read) {
+ if (!spi_programmer->read) {
msg_perr("%s called, but SPI read is unsupported on this "
"hardware. Please report a bug at "
"flashrom(a)flashrom.org\n", __func__);
@@ -308,7 +150,7 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
"access window.\n");
msg_perr("Read will probably return garbage.\n");
}
- return spi_programmer[spi_controller].read(flash, buf, addrbase + start, len);
+ return spi_programmer->read(flash, buf, addrbase + start, len);
}
/*
@@ -320,14 +162,14 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
/* real chunksize is up to 256, logical chunksize is 256 */
int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len)
{
- if (!spi_programmer[spi_controller].write_256) {
+ if (!spi_programmer->write_256) {
msg_perr("%s called, but SPI page write is unsupported on this "
"hardware. Please report a bug at "
"flashrom(a)flashrom.org\n", __func__);
return 1;
}
- return spi_programmer[spi_controller].write_256(flash, buf, start, len);
+ return spi_programmer->write_256(flash, buf, start, len);
}
/*
@@ -337,7 +179,7 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len
*/
uint32_t spi_get_valid_read_addr(void)
{
- switch (spi_controller) {
+ switch (spi_programmer->type) {
#if CONFIG_INTERNAL == 1
#if defined(__i386__) || defined(__x86_64__)
case SPI_CONTROLLER_ICH7:
@@ -349,3 +191,9 @@ uint32_t spi_get_valid_read_addr(void)
return 0;
}
}
+
+void register_spi_programmer(const struct spi_programmer *pgm)
+{
+ spi_programmer = pgm;
+ buses_supported |= CHIP_BUSTYPE_SPI;
+}
\ No newline at end of file
diff --git a/spi25.c b/spi25.c
index c9e1ebf..b3bd7a1 100644
--- a/spi25.c
+++ b/spi25.c
@@ -178,7 +178,7 @@ int probe_spi_rdid4(struct flashchip *flash)
/* Some SPI controllers do not support commands with writecnt=1 and
* readcnt=4.
*/
- switch (spi_controller) {
+ switch (spi_programmer->type) {
#if CONFIG_INTERNAL == 1
#if defined(__i386__) || defined(__x86_64__)
case SPI_CONTROLLER_IT87XX:
@@ -1351,7 +1351,7 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len)
.readarr = NULL,
}};
- switch (spi_controller) {
+ switch (spi_programmer->type) {
#if CONFIG_INTERNAL == 1
#if defined(__i386__) || defined(__x86_64__)
case SPI_CONTROLLER_IT87XX:
diff --git a/wbsio_spi.c b/wbsio_spi.c
index 12c458e..734732e 100644
--- a/wbsio_spi.c
+++ b/wbsio_spi.c
@@ -50,7 +50,7 @@ static uint16_t wbsio_spibase = 0;
* Would one more byte of RAM in the chip (to get all 24 bits) really make
* such a big difference?
*/
-int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt,
+static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr)
{
int i;
@@ -134,7 +134,7 @@ int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt,
return 0;
}
-int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len)
+static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len)
{
return read_memmapped(flash, buf, start, len);
}
@@ -169,6 +169,16 @@ done:
return flashport;
}
+static const struct spi_programmer spi_programmer_wbsio = {
+ .type = SPI_CONTROLLER_WBSIO,
+ .max_data_read = MAX_DATA_UNSPECIFIED,
+ .max_data_write = MAX_DATA_UNSPECIFIED,
+ .command = wbsio_spi_send_command,
+ .multicommand = default_spi_send_multicommand,
+ .read = wbsio_spi_read,
+ .write_256 = spi_chip_write_1,
+};
+
int wbsio_check_for_spi(void)
{
if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1)))
@@ -177,8 +187,7 @@ int wbsio_check_for_spi(void)
msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase);
- buses_supported |= CHIP_BUSTYPE_SPI;
- spi_controller = SPI_CONTROLLER_WBSIO;
+ register_spi_programmer(&spi_programmer_wbsio);
msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is "
"1024 KB!\n", __func__);
max_rom_decode.spi = 1024 * 1024;
--
1.7.4.1
