flashrom February 2011

flashrom@flashrom.org

37 participants
119 discussions

As instructed by flashrom_bot
by Schnittchen 17 Feb '11

17 Feb '11

See pastie links. Hope it helps. Keep up the good work! Schnittchen Your paste can be seen at http://paste.flashrom.org/view.php?id=355 Your upload can be seen at http://paste.flashrom.org/view.php?id=356

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Re: [flashrom] [coreboot] Tester devices [was: QA contribution]
by Carl-Daniel Hailfinger 17 Feb '11

17 Feb '11

Hi Juhana, I've added the flashrom mailing list to CC. Auf 12.02.2011 19:55, Juhana Helovuo schrieb: > Now there is more progress. After some building, coding, and debugging > I have the tester sort-of-working. > > The first version of the hardware works. > > In this image you can see the tester plugged into an Asus mainboard: > > http://alpskari.asiantuntijat.org/~juhe/in-system-flasher/DSC08430.jpg > > Today I successfully used this setup to reflash the mainboard from the > host PC via flashrom. > > The USB cable goes to a host computer, which is running a modified > flashrom program. The flashrom is extended with a serprog_spi module, > which can transfer SPI over the serprog protocol, and additionally > toggle SPI bus multiplexer between the MCU and mainboard at the > beginning and end of programming. > > The tester hardware has the following features: > > * Tester can access the ROM also when disconnected from the target > mainboard. > > The work is still quite incomplete: > > * Currently there is no tester firmware that could operate both the > SPI and RS-232. The main problem is that the AT90USB162 > microcontroller supports only up to five USB endpoints (including > default control EP). I do not know if it is possible to implement two > USB CDC class virtual serial ports with less than seven EPs. With two > serial ports, one could represent the RS-232 interface, and other be > used to control the programmer without writing any custom USB drivers. > > This could be solved either in software by writing a custom USB driver > for both the tester and the host, or in hardware by replacing the > microcontroller with a more capable model. If anyone on the list can > suggest any easier solutions, I'd be glad to hear about them. > > * The handling of SPI ROM is horribly slow. Programming and verifying > 1 MByte ROM takes about half an hour. The main suspect is nonexistent > USB data buffering in the tester firmware. There are a few tricks we could use to speed up SPI programming with your hardware. flashrom already supports the Dediprog SF100 USB-based SPI programmer, and that works well. Maybe we could use a similar communication protocol, and/or use a serprog-like protocol directly on top of libusb without the need of serial port emulation. The serial port emulation is probably the biggest reason why anything is slow. If you tell me about the design constraints of your device, I can probably come up with a flashrom driver which can reflash an 1 MByte ROM in ~5 minutes or so. That will require some cooperation from your device, but should be doable with ~270 bytes of RAM. Even with ~140 bytes of RAM we should be able to get some decent performance. As long as we can optimize the protocol, it should be possible to get acceptable performance even with only 50 bytes of RAM, but generally more RAM will give you better performance. Side note: I think there once was a SPI-serprog design on the flashrom mailing list, but I can't find it right now. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH] Support 64-bit MEM BARs
by Carl-Daniel Hailfinger 15 Feb '11

15 Feb '11

Support 64-bit MEM BARs wherever possible. Add more sanity checks for BARs and abort if resources are unreachable. Undecoded resources are reported, but flashrom will proceed anyway just in case the BIOS screwed up the configuration. (The empty CardBus handler is intentional, according to the spec no BARs in PCI config space are used by CardBus.) Verbose logs (and tests) with PCI-based external programmers would be highly appreciated. I spotted this while working on a driver for a PCIe-based SSD which has 64-bit capable MEM BARs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-64bit_membar/pcidev.c =================================================================== --- flashrom-64bit_membar/pcidev.c (Revision 1257) +++ flashrom-64bit_membar/pcidev.c (Arbeitskopie) @@ -2,6 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2010, 2011 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,43 +28,151 @@ struct pci_access *pacc; struct pci_dev *pcidev_dev = NULL; -uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, +enum pci_bartype { + TYPE_MEMBAR, + TYPE_IOBAR, + TYPE_ROMBAR, + TYPE_UNKNOWN +}; + +uintptr_t pcidev_validate(struct pci_dev *dev, int bar, const struct pcidev_status *devs) { int i; - /* FIXME: 64 bit memory BARs need a 64 bit addr. */ - uint32_t addr; + uint64_t addr; + uint32_t upperaddr; + uint8_t headertype; + uint16_t supported_cycles; + enum pci_bartype bartype = TYPE_UNKNOWN; for (i = 0; devs[i].device_name != NULL; i++) { if (dev->device_id != devs[i].device_id) continue; + msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", + devs[i].vendor_name, devs[i].device_name, + dev->vendor_id, dev->device_id, dev->bus, dev->dev, + dev->func); + + headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f; + msg_pspew("PCI header type 0x%02x\n", headertype); + /* * Don't use dev->base_addr[x] (as value for 'bar'), won't * work on older libpci. */ addr = pci_read_long(dev, bar); - - msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", - devs[i].vendor_name, devs[i].device_name, - dev->vendor_id, dev->device_id, dev->bus, dev->dev, - dev->func); - msg_pdbg("Requested BAR is %s", (addr & 0x1) ? "IO" : "MEM"); - if (addr & 0x1) { - /* Mask off IO space indicator and reserved bit. */ - msg_pdbg("\n"); - addr &= ~0x3; - } else { + + /* Sanity checks. */ + switch (headertype) { + case PCI_HEADER_TYPE_NORMAL: + switch (bar) { + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: + case PCI_BASE_ADDRESS_2: + case PCI_BASE_ADDRESS_3: + case PCI_BASE_ADDRESS_4: + case PCI_BASE_ADDRESS_5: + if ((addr & PCI_BASE_ADDRESS_SPACE) == + PCI_BASE_ADDRESS_SPACE_IO) + bartype = TYPE_IOBAR; + else + bartype = TYPE_MEMBAR; + break; + case PCI_ROM_ADDRESS: + bartype = TYPE_ROMBAR; + break; + } + break; + case PCI_HEADER_TYPE_BRIDGE: + switch (bar) { + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: + if ((addr & PCI_BASE_ADDRESS_SPACE) == + PCI_BASE_ADDRESS_SPACE_IO) + bartype = TYPE_IOBAR; + else + bartype = TYPE_MEMBAR; + break; + case PCI_ROM_ADDRESS1: + bartype = TYPE_ROMBAR; + break; + } + break; + case PCI_HEADER_TYPE_CARDBUS: + break; + default: + msg_perr("Unknown PCI header type 0x%02x, BAR type " + "cannot be determined reliably.\n", headertype); + break; + } + + supported_cycles = pci_read_word(dev, PCI_COMMAND); + + msg_pdbg("Requested BAR is "); + switch (bartype) { + case TYPE_MEMBAR: + msg_pdbg("MEM"); + if (!(supported_cycles & PCI_COMMAND_MEMORY)) { + msg_perr("MEM BAR access requested, but device " + "has MEM space accesses disabled.\n"); + /* TODO: Abort here? */ + } msg_pdbg(", %sbit, %sprefetchable\n", ((addr & 0x6) == 0x0) ? "32" : (((addr & 0x6) == 0x4) ? "64" : "reserved"), (addr & 0x8) ? "" : "not "); - /* Mask off Mem space indicator, 32/64bit type indicator - * and Prefetchable indicator. - */ - addr &= ~0xf; + if ((addr & 0x6) == 0x4) { + /* The spec says that a 64-bit register consumes + * two subsequent dword locations. + */ + upperaddr = pci_read_long(dev, bar + 4); + if (upperaddr != 0x00000000) { + /* Fun! A real 64-bit resource. */ + if (sizeof(uintptr_t) != sizeof(uint64_t)) { + msg_perr("BAR unreachable!"); + /* TODO: Really abort here? If + * multiple PCI devices match, + * we might never tell the user + * about the other devices. + */ + return 0; + } + addr |= (uint64_t)upperaddr << 32; + } + } + addr &= PCI_BASE_ADDRESS_MEM_MASK; + break; + case TYPE_IOBAR: + msg_pdbg("I/O\n"); +#if __FLASHROM_HAVE_OUTB__ + if (!(supported_cycles & PCI_COMMAND_IO)) { + msg_perr("I/O BAR access requested, but device " + "has I/O space accesses disabled.\n"); + /* TODO: Abort here? */ + } +#else + msg_perr("I/O BAR access requested, but flashrom does " + "not support I/O BAR access on this platform " + "(yet).\n"); +#endif + addr &= PCI_BASE_ADDRESS_IO_MASK; + break; + case TYPE_ROMBAR: + msg_pdbg("ROM\n"); + /* Not sure if this check is needed. */ + if (!(supported_cycles & PCI_COMMAND_MEMORY)) { + msg_perr("MEM BAR access requested, but device " + "has MEM space accesses disabled.\n"); + /* TODO: Abort here? */ + } + addr &= PCI_ROM_ADDRESS_MASK; + break; + case TYPE_UNKNOWN: + msg_perr("BAR type unknown, please report a bug at " + "flashrom(a)flashrom.org\n"); } - + if (devs[i].status == NT) { msg_pinfo("===\nThis PCI device is UNTESTED. Please " "report the 'flashrom -p xxxx' output \n" @@ -73,13 +182,13 @@ "your help!\n===\n"); } - return addr; + return (uintptr_t)addr; } return 0; } -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, +uintptr_t pcidev_init(uint16_t vendor_id, int bar, const struct pcidev_status *devs) { struct pci_dev *dev; @@ -87,7 +196,7 @@ char *pcidev_bdf; char *msg = NULL; int found = 0; - uint32_t addr = 0, curaddr = 0; + uintptr_t addr = 0, curaddr = 0; pacc = pci_alloc(); /* Get the pci_access structure */ pci_init(pacc); /* Initialize the PCI library */ Index: flashrom-64bit_membar/programmer.h =================================================================== --- flashrom-64bit_membar/programmer.h (Revision 1257) +++ flashrom-64bit_membar/programmer.h (Arbeitskopie) @@ -216,8 +216,8 @@ const char *vendor_name; const char *device_name; }; -uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, const struct pcidev_status *devs); -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, const struct pcidev_status *devs); +uintptr_t pcidev_validate(struct pci_dev *dev, int bar, const struct pcidev_status *devs); +uintptr_t pcidev_init(uint16_t vendor_id, int bar, const struct pcidev_status *devs); /* rpci_write_* are reversible writes. The original PCI config space register * contents will be restored on shutdown. */ -- http://www.hailfinger.org/

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[commit] r1261 - trunk
by repository service 15 Feb '11

15 Feb '11

Author: hailfinger Date: Tue Feb 15 23:44:27 2011 New Revision: 1261 URL: http://flashrom.org/trac/flashrom/changeset/1261 Log: Support 64-bit MEM BARs wherever possible. Add more sanity checks for BARs and abort if resources are unreachable. Undecoded resources are reported, but flashrom will proceed anyway just in case the BIOS screwed up the configuration. (The empty CardBus handler is intentional, according to the spec no BARs in PCI config space are used by CardBus.) Found while working on a driver for the Angelbird PCIe-based SSD which has 64-bit capable MEM BARs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/pcidev.c trunk/programmer.h Modified: trunk/pcidev.c ============================================================================== --- trunk/pcidev.c Sat Feb 5 13:11:17 2011 (r1260) +++ trunk/pcidev.c Tue Feb 15 23:44:27 2011 (r1261) @@ -2,6 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2010, 2011 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,43 +28,151 @@ struct pci_access *pacc; struct pci_dev *pcidev_dev = NULL; -uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, +enum pci_bartype { + TYPE_MEMBAR, + TYPE_IOBAR, + TYPE_ROMBAR, + TYPE_UNKNOWN +}; + +uintptr_t pcidev_validate(struct pci_dev *dev, int bar, const struct pcidev_status *devs) { int i; - /* FIXME: 64 bit memory BARs need a 64 bit addr. */ - uint32_t addr; + uint64_t addr; + uint32_t upperaddr; + uint8_t headertype; + uint16_t supported_cycles; + enum pci_bartype bartype = TYPE_UNKNOWN; for (i = 0; devs[i].device_name != NULL; i++) { if (dev->device_id != devs[i].device_id) continue; + msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", + devs[i].vendor_name, devs[i].device_name, + dev->vendor_id, dev->device_id, dev->bus, dev->dev, + dev->func); + + headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f; + msg_pspew("PCI header type 0x%02x\n", headertype); + /* * Don't use dev->base_addr[x] (as value for 'bar'), won't * work on older libpci. */ addr = pci_read_long(dev, bar); - - msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", - devs[i].vendor_name, devs[i].device_name, - dev->vendor_id, dev->device_id, dev->bus, dev->dev, - dev->func); - msg_pdbg("Requested BAR is %s", (addr & 0x1) ? "IO" : "MEM"); - if (addr & 0x1) { - /* Mask off IO space indicator and reserved bit. */ - msg_pdbg("\n"); - addr &= ~0x3; - } else { + + /* Sanity checks. */ + switch (headertype) { + case PCI_HEADER_TYPE_NORMAL: + switch (bar) { + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: + case PCI_BASE_ADDRESS_2: + case PCI_BASE_ADDRESS_3: + case PCI_BASE_ADDRESS_4: + case PCI_BASE_ADDRESS_5: + if ((addr & PCI_BASE_ADDRESS_SPACE) == + PCI_BASE_ADDRESS_SPACE_IO) + bartype = TYPE_IOBAR; + else + bartype = TYPE_MEMBAR; + break; + case PCI_ROM_ADDRESS: + bartype = TYPE_ROMBAR; + break; + } + break; + case PCI_HEADER_TYPE_BRIDGE: + switch (bar) { + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: + if ((addr & PCI_BASE_ADDRESS_SPACE) == + PCI_BASE_ADDRESS_SPACE_IO) + bartype = TYPE_IOBAR; + else + bartype = TYPE_MEMBAR; + break; + case PCI_ROM_ADDRESS1: + bartype = TYPE_ROMBAR; + break; + } + break; + case PCI_HEADER_TYPE_CARDBUS: + break; + default: + msg_perr("Unknown PCI header type 0x%02x, BAR type " + "cannot be determined reliably.\n", headertype); + break; + } + + supported_cycles = pci_read_word(dev, PCI_COMMAND); + + msg_pdbg("Requested BAR is "); + switch (bartype) { + case TYPE_MEMBAR: + msg_pdbg("MEM"); + if (!(supported_cycles & PCI_COMMAND_MEMORY)) { + msg_perr("MEM BAR access requested, but device " + "has MEM space accesses disabled.\n"); + /* TODO: Abort here? */ + } msg_pdbg(", %sbit, %sprefetchable\n", ((addr & 0x6) == 0x0) ? "32" : (((addr & 0x6) == 0x4) ? "64" : "reserved"), (addr & 0x8) ? "" : "not "); - /* Mask off Mem space indicator, 32/64bit type indicator - * and Prefetchable indicator. - */ - addr &= ~0xf; + if ((addr & 0x6) == 0x4) { + /* The spec says that a 64-bit register consumes + * two subsequent dword locations. + */ + upperaddr = pci_read_long(dev, bar + 4); + if (upperaddr != 0x00000000) { + /* Fun! A real 64-bit resource. */ + if (sizeof(uintptr_t) != sizeof(uint64_t)) { + msg_perr("BAR unreachable!"); + /* TODO: Really abort here? If + * multiple PCI devices match, + * we might never tell the user + * about the other devices. + */ + return 0; + } + addr |= (uint64_t)upperaddr << 32; + } + } + addr &= PCI_BASE_ADDRESS_MEM_MASK; + break; + case TYPE_IOBAR: + msg_pdbg("I/O\n"); +#if __FLASHROM_HAVE_OUTB__ + if (!(supported_cycles & PCI_COMMAND_IO)) { + msg_perr("I/O BAR access requested, but device " + "has I/O space accesses disabled.\n"); + /* TODO: Abort here? */ + } +#else + msg_perr("I/O BAR access requested, but flashrom does " + "not support I/O BAR access on this platform " + "(yet).\n"); +#endif + addr &= PCI_BASE_ADDRESS_IO_MASK; + break; + case TYPE_ROMBAR: + msg_pdbg("ROM\n"); + /* Not sure if this check is needed. */ + if (!(supported_cycles & PCI_COMMAND_MEMORY)) { + msg_perr("MEM BAR access requested, but device " + "has MEM space accesses disabled.\n"); + /* TODO: Abort here? */ + } + addr &= PCI_ROM_ADDRESS_MASK; + break; + case TYPE_UNKNOWN: + msg_perr("BAR type unknown, please report a bug at " + "flashrom(a)flashrom.org\n"); } - + if (devs[i].status == NT) { msg_pinfo("===\nThis PCI device is UNTESTED. Please " "report the 'flashrom -p xxxx' output \n" @@ -73,13 +182,13 @@ "your help!\n===\n"); } - return addr; + return (uintptr_t)addr; } return 0; } -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, +uintptr_t pcidev_init(uint16_t vendor_id, int bar, const struct pcidev_status *devs) { struct pci_dev *dev; @@ -87,7 +196,7 @@ char *pcidev_bdf; char *msg = NULL; int found = 0; - uint32_t addr = 0, curaddr = 0; + uintptr_t addr = 0, curaddr = 0; pacc = pci_alloc(); /* Get the pci_access structure */ pci_init(pacc); /* Initialize the PCI library */ Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sat Feb 5 13:11:17 2011 (r1260) +++ trunk/programmer.h Tue Feb 15 23:44:27 2011 (r1261) @@ -219,8 +219,8 @@ const char *vendor_name; const char *device_name; }; -uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, const struct pcidev_status *devs); -uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, const struct pcidev_status *devs); +uintptr_t pcidev_validate(struct pci_dev *dev, int bar, const struct pcidev_status *devs); +uintptr_t pcidev_init(uint16_t vendor_id, int bar, const struct pcidev_status *devs); /* rpci_write_* are reversible writes. The original PCI config space register * contents will be restored on shutdown. */

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Intel NIC flashrom fail
by Антон Кочков 15 Feb '11

15 Feb '11

flashrom -r INTEL.ROM -p nicintel_spi:pci=02:0B.0 -VV flashrom v0.9.3-r1250 on MS-DOS 8 (i786), built with libpci 3.1.5, GCC 4.3.2, little endian flashrom is free software, get the source code at flashrom.org Calibrating delay loop... OS timer resolution is 50000 usecs, 1589M loops per second, 10 myus = 0 us, 100 myus = 0 us, 1000 myus = 0 us, 10000 myus = 0 us, 200000 myus = 220000 us, OK. Initializing nicintel_spi programmer ERROR: No supported PCI device found lspci output: http://paste.flashrom.org/view.php?id=347 vendor flash tool: http://paste.flashrom.org/view.php?id=348 Best regards, Anton Kochkov.

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Read/Fast Read chip status sheet (re-send)
by Steven Zakulec 12 Feb '11

12 Feb '11

(I'm re-sending this now because carldani asked if I could re-send it after FOSDEM). Hi, here's a copy of the sheet I created covering most of the chips (it's the same chip list as in my previous list- the form factor & voltage one). If I couldn't figure out whether the chip had read/fast read, I left it blank. Otherwise, I filled in on the sheet the instruction code, any notes, and whether the mode(s) on the datasheet were the ones Flashrom wanted.

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mx25l8005 write report
by Alec Wright 12 Feb '11

12 Feb '11

Apparently it's been marked as untested again

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EVGA nForce 780i Revised
by Brandon Dowdy 10 Feb '11

10 Feb '11

Manufacturer: EVGA Model: nForce 780i Super I/O: Winbond W83627DHG Flash chip: SST SST49LF080A Southbridge: NVIDIA MCP55 I don't know what the northbridge for the board is, so that's one more thing to find before coreboot fully supports it. acpidump output included. P.S. Sorry if the email is too big like the last one. And also, The only difference is that the logs are updated and some more logs are added.

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Re: [flashrom] Vortex86 based machines
by Антон Кочков 10 Feb '11

10 Feb '11

Full developer manual and additional information available here http://www.dmp.com.tw/tech/vortex86dx/ 2011/2/10 Антон Кочков <anton.kochkov(a)gmail.com>: > Here an suggestion of some cheap nettop. > It use SPI flash and winbond super i/o. > Attached log of proprietary utility and documentation (software > reference manual) > > original spiflash utility (for DOS) can be downloaded here > http://rghost.net/4282595 > > -- > Best regards, > Anton Kochkov. > -- Best regards, Anton Kochkov.

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FAILED: Asus P5NSLI
by Alvaro Aguilera 06 Feb '11

06 Feb '11

Hello, I'm trying to update the BIOS of a P5NSLI board but the procedure failed. Any hints on how to correct this? Thanks, Alvaro.

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flashrom February 2011