flashrom February 2011

flashrom@flashrom.org

37 participants
119 discussions

Flashrom Winbond W25Q64 Erase and write support works
by Юшаков Дмитрий 06 Feb '11

06 Feb '11

Hello, flashrom team. I just flashed on my P5Q deluxe motherboard with ICH10R SB EPPROM from my new ASRock p67 extreme4 board, it's Winbond W25Q64. In your support table it's '?' for erase and write, so it works greatly. Thank you for your util. But some binaries for dos can save time for users and increase popularity for you utility. That was too hard for me to install latest version on Ubuntu live USB. Best regards!

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[PATCH] Add support for AMD Am29LV00*
by Carl-Daniel Hailfinger 05 Feb '11

05 Feb '11

Add support for AMD Am29LV001BB, Am29LV001BT, Am29LV002BB, Am29LV002BT, Am29LV004BB, Am29LV004BT, Am29LV008BB, Am29LV008BT Mark, could you please update a clean tree to latest flashrom (which has the Angelbird SSD support) and apply this patch on top? It should recognize your flash chip, and allow read/write/erase without the need to specify -f. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-am29lv00x/flashchips.c =================================================================== --- flashrom-am29lv00x/flashchips.c (Revision 1258) +++ flashrom-am29lv00x/flashchips.c (Arbeitskopie) @@ -224,6 +224,252 @@ { .vendor = "AMD", + .name = "Am29LV001BB", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV001BB, + .total_size = 128, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {8 * 1024, 1}, + {4 * 1024, 2}, + {16 * 1024, 7}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV001BT", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV001BT, + .total_size = 128, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 7}, + {4 * 1024, 2}, + {8 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV002BB", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV002BB, + .total_size = 256, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {32 * 1024, 1}, + {64 * 1024, 3}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV002BT", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV002BT, + .total_size = 256, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 3}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV004BB", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV004BB, + .total_size = 512, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {32 * 1024, 1}, + {64 * 1024, 7}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV004BT", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV004BT, + .total_size = 512, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 7}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV008BB", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV008BB, + .total_size = 1024, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {32 * 1024, 1}, + {64 * 1024, 15}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV008BT", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV008BT, + .total_size = 1024, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 15}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", .name = "Am29LV040B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMD_ID, Index: flashrom-am29lv00x/flashchips.h =================================================================== --- flashrom-am29lv00x/flashchips.h (Revision 1258) +++ flashrom-am29lv00x/flashchips.h (Arbeitskopie) @@ -70,6 +70,8 @@ #define AMD_AM29F400BT 0x23 #define AMD_AM29F800BB 0x58 #define AMD_AM29F800BT 0xD6 +#define AMD_AM29LV001BB 0x6D +#define AMD_AM29LV001BT 0xED #define AMD_AM29LV002BB 0xC2 #define AMD_AM29LV002BT 0x40 #define AMD_AM29LV004BB 0xB6 -- http://www.hailfinger.org/

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[commit] r1260 - trunk
by repository service 05 Feb '11

05 Feb '11

Author: hailfinger Date: Sat Feb 5 13:11:17 2011 New Revision: 1260 URL: http://flashrom.org/trac/flashrom/changeset/1260 Log: Add support for AMD Am29LV001BB, Am29LV001BT, Am29LV002BB, Am29LV002BT, Am29LV004BB, Am29LV004BT, Am29LV008BB, Am29LV008BT Thanks to Mark Pustjens for testing the Am29LV001BB. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Fri Feb 4 23:52:04 2011 (r1259) +++ trunk/flashchips.c Sat Feb 5 13:11:17 2011 (r1260) @@ -224,6 +224,252 @@ { .vendor = "AMD", + .name = "Am29LV001BB", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV001BB, + .total_size = 128, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_OK_PREW, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {8 * 1024, 1}, + {4 * 1024, 2}, + {16 * 1024, 7}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV001BT", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV001BT, + .total_size = 128, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 7}, + {4 * 1024, 2}, + {8 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV002BB", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV002BB, + .total_size = 256, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {32 * 1024, 1}, + {64 * 1024, 3}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV002BT", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV002BT, + .total_size = 256, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 3}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV004BB", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV004BB, + .total_size = 512, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {32 * 1024, 1}, + {64 * 1024, 7}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV004BT", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV004BT, + .total_size = 512, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 7}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV008BB", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV008BB, + .total_size = 1024, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {32 * 1024, 1}, + {64 * 1024, 15}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", + .name = "Am29LV008BT", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AMD_AM29LV008BT, + .total_size = 1024, + .page_size = 64 * 1024, /* unused */ + .feature_bits = FEATURE_ADDR_2AA | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 15}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "AMD", .name = "Am29LV040B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMD_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Fri Feb 4 23:52:04 2011 (r1259) +++ trunk/flashchips.h Sat Feb 5 13:11:17 2011 (r1260) @@ -70,6 +70,8 @@ #define AMD_AM29F400BT 0x23 #define AMD_AM29F800BB 0x58 #define AMD_AM29F800BT 0xD6 +#define AMD_AM29LV001BB 0x6D +#define AMD_AM29LV001BT 0xED #define AMD_AM29LV002BB 0xC2 #define AMD_AM29LV002BT 0x40 #define AMD_AM29LV004BB 0xB6

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Giada N3, flashrom -Vr
by Tristan Plumb 04 Feb '11

04 Feb '11

Note, I have a few of these and soldering skills, and will happily test writing to the flash if so desired. The dumped rom is valid. flashrom v0.9.3-r1258 on Linux 2.6.27.8 (i686), built with libpci 2.2.10, GCC 4.2.4, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 3 usecs, 798M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 999 us, 10000 myus = 10021 us, 12 myus = 14 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "To Be Filled By O.E.M." DMI string system-product-name: "To Be Filled By O.E.M." DMI string system-version: "To Be Filled By O.E.M." DMI string baseboard-manufacturer: "ASL" DMI string baseboard-product-name: "MCP7A-ION" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP79", enabling flash write... chipset PCI ID is 10de:0aad, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI Found SMBus device 10de:0aa2 at 00:03:2 MCP SPI BAR is at 0xfae80000 SPI control is 0xc052, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L16PT, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L16PU, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for Bright BM29F040, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Hyundai HY29F040A, 512 KB: skipped. Probing for Intel 28F001BN/BX-B, 128 KB: skipped. Probing for Intel 28F001BN/BX-T, 128 KB: skipped. Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped. Probing for Intel 28F008S3/S5/SC, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1635E, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29F040, 512 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL004A, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL032A, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL064A, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF010.REMS, 128 KB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25PX32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25PX64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Chip status register is 00 Found chip "Winbond W25x80" (1024 KB, SPI) at physical address 0xfff00000. Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped. Probing for Winbond W29C040/P, 512 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V040FB, 512 KB: skipped. Probing for Winbond W39V040FC, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U/N, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for AMIC unknown AMIC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xef, id2 0x13 === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Reading flash... done.

1 0

[commit] r1259 - trunk
by repository service 04 Feb '11

04 Feb '11

Author: hailfinger Date: Fri Feb 4 23:52:04 2011 New Revision: 1259 URL: http://flashrom.org/trac/flashrom/changeset/1259 Log: Improve debugging for unaligned erase in the flash chip emulator. Fix out-of-bounds access for chip erase in the flash chip emulator. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: David Hendricks <dhendrix(a)google.com> Modified: trunk/dummyflasher.c Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Fri Feb 4 22:37:59 2011 (r1258) +++ trunk/dummyflasher.c Fri Feb 4 23:52:04 2011 (r1259) @@ -395,7 +395,7 @@ } offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; if (offs & (emu_jedec_se_size - 1)) - msg_pdbg("Unaligned SECTOR ERASE 0x20\n"); + msg_pdbg("Unaligned SECTOR ERASE 0x20: 0x%x\n", offs); offs &= ~(emu_jedec_se_size - 1); memset(flashchip_contents + offs, 0xff, emu_jedec_se_size); break; @@ -412,7 +412,7 @@ } offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; if (offs & (emu_jedec_be_52_size - 1)) - msg_pdbg("Unaligned BLOCK ERASE 0x52\n"); + msg_pdbg("Unaligned BLOCK ERASE 0x52: 0x%x\n", offs); offs &= ~(emu_jedec_be_52_size - 1); memset(flashchip_contents + offs, 0xff, emu_jedec_be_52_size); break; @@ -429,7 +429,7 @@ } offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; if (offs & (emu_jedec_be_d8_size - 1)) - msg_pdbg("Unaligned BLOCK ERASE 0xd8\n"); + msg_pdbg("Unaligned BLOCK ERASE 0xd8: 0x%x\n", offs); offs &= ~(emu_jedec_be_d8_size - 1); memset(flashchip_contents + offs, 0xff, emu_jedec_be_d8_size); break; @@ -444,12 +444,9 @@ msg_perr("CHIP ERASE 0x60 insize invalid!\n"); return 1; } - offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; - if (offs & (emu_jedec_ce_60_size - 1)) - msg_pdbg("Unaligned CHIP ERASE 0x60\n"); - offs &= ~(emu_jedec_ce_60_size - 1); + /* JEDEC_CE_60_OUTSIZE is 1 (no address) -> no offset. */ /* emu_jedec_ce_60_size is emu_chip_size. */ - memset(flashchip_contents + offs, 0xff, emu_jedec_ce_60_size); + memset(flashchip_contents, 0xff, emu_jedec_ce_60_size); break; case JEDEC_CE_C7: if (!emu_jedec_ce_c7_size) @@ -462,10 +459,7 @@ msg_perr("CHIP ERASE 0xc7 insize invalid!\n"); return 1; } - offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; - if (offs & (emu_jedec_ce_c7_size - 1)) - msg_pdbg("Unaligned CHIP ERASE 0xc7\n"); - offs &= ~(emu_jedec_ce_c7_size - 1); + /* JEDEC_CE_C7_OUTSIZE is 1 (no address) -> no offset. */ /* emu_jedec_ce_c7_size is emu_chip_size. */ memset(flashchip_contents, 0xff, emu_jedec_ce_c7_size); break;

1 0

[PATCH] Support for Angelbird Wings PCIe SSD, Marvell 88SX7042
by Carl-Daniel Hailfinger 04 Feb '11

04 Feb '11

Support for Angelbird Wings PCIe SSD (solid-state drive). It uses a Marvell 88SX7042 SATA controller internally which has access to a separate flash chip hosting the option ROM. Thanks to Angelbird Ltd for sponsoring development of this driver! I expect the code to work for that SATA controller even if it is not part of the Angelbird SSD. Note: The controller has 64-bit BARs which may be mapped outside the 32-bit (4 GB) address space. A separate patch has been sent to fix that code. Tested on hardware. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-marvell/satamv.c =================================================================== --- flashrom-marvell/satamv.c (Revision 0) +++ flashrom-marvell/satamv.c (Revision 0) @@ -0,0 +1,183 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010,2011 Carl-Daniel Hailfinger + * Written by Carl-Daniel Hailfinger for Angelbird Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Datasheets are not public (yet?) */ + +#include <stdlib.h> +#include "flash.h" +#include "programmer.h" + +uint8_t *mv_bar; +uint16_t mv_iobar; + +const struct pcidev_status satas_mv[] = { + /* 88SX6041 and 88SX6042 are the same according to the datasheet. */ + {0x11ab, 0x7042, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II"}, + + {}, +}; + +#define NVRAM_PARAM 0x1045c +#define FLASH_PARAM 0x1046c +#define EXPANSION_ROM_BAR_CONTROL 0x00d2c +#define PCI_BAR2_CONTROL 0x00c08 +#define GPIO_PORT_CONTROL 0x104f0 + +/* + * Random notes: + * FCE# Flash Chip Enable + * FWE# Flash Write Enable + * FOE# Flash Output Enable + * FALE[1:0] Flash Address Latch Enable + * FAD[7:0] Flash Multiplexed Address/Data Bus + * FA[2:0] Flash Address Low + * + * GPIO[15,2] GPIO Port Mode + * GPIO[4:3] Flash Size + * + * 0xd2c Expansion ROM BAR Control + * 0xc08 PCI BAR2 (Flash/NVRAM) Control + * 0x1046c Flash Parameters + */ +int satamv_init(void) +{ + uintptr_t addr; + uint32_t tmp; + + get_io_perms(); + + /* BAR0 has all internal registers memory mapped. */ + /* No need to check for errors, pcidev_init() will not return in case + * of errors. + */ + addr = pcidev_init(0x11ab, PCI_BASE_ADDRESS_0, satas_mv); + + mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000); + if (mv_bar == ERROR_PTR) + goto error_out; + + tmp = pci_mmio_readl(mv_bar + FLASH_PARAM); + msg_pspew("Flash Parameters:\n"); + msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7); + msg_pspew("Acc2First=0x%01x\n", (tmp >> 3) & 0xf); + msg_pspew("Acc2Next=0x%01x\n", (tmp >> 7) & 0xf); + msg_pspew("ALE2Wr=0x%01x\n", (tmp >> 11) & 0x7); + msg_pspew("WrLow=0x%01x\n", (tmp >> 14) & 0x7); + msg_pspew("WrHigh=0x%01x\n", (tmp >> 17) & 0x7); + msg_pspew("Reserved[21:20]=0x%01x\n", (tmp >> 20) & 0x3); + msg_pspew("TurnOffExt=0x%01x\n", (tmp >> 22) & 0x1); + msg_pspew("Acc2FirstExt=0x%01x\n", (tmp >> 23) & 0x1); + msg_pspew("Acc2NextExt=0x%01x\n", (tmp >> 24) & 0x1); + msg_pspew("ALE2WrExt=0x%01x\n", (tmp >> 25) & 0x1); + msg_pspew("WrLowExt=0x%01x\n", (tmp >> 26) & 0x1); + msg_pspew("WrHighExt=0x%01x\n", (tmp >> 27) & 0x1); + msg_pspew("Reserved[31:28]=0x%01x\n", (tmp >> 28) & 0xf); + + tmp = pci_mmio_readl(mv_bar + EXPANSION_ROM_BAR_CONTROL); + msg_pspew("Expansion ROM BAR Control:\n"); + msg_pspew("ExpROMSz=0x%01x\n", (tmp >> 19) & 0x7); + + /* Enable BAR2 mapping to flash */ + tmp = pci_mmio_readl(mv_bar + PCI_BAR2_CONTROL); + msg_pspew("PCI BAR2 (Flash/NVRAM) Control:\n"); + msg_pspew("Bar2En=0x%01x\n", (tmp >> 0) & 0x1); + msg_pspew("BAR2TransAttr=0x%01x\n", (tmp >> 1) & 0x1f); + msg_pspew("BAR2Sz=0x%01x\n", (tmp >> 19) & 0x7); + tmp &= 0xffffffc0; + tmp |= 0x0000001f; + /* FIXME: This needs to be an auto-reversible write. */ + pci_mmio_writel(tmp, mv_bar + PCI_BAR2_CONTROL); + + /* Enable flash: GPIO Port Control Register 0x104f0 */ + tmp = pci_mmio_readl(mv_bar + GPIO_PORT_CONTROL); + msg_pspew("GPIOPortMode=0x%01x\n", (tmp >> 0) & 0x3); + if (((tmp >> 0) & 0x3) != 0x2) + msg_pinfo("Warning! Either the straps are incorrect or you " + "have no flash or someone overwrote the strap " + "values!\n"); + tmp &= 0xfffffffc; + tmp |= 0x2; + /* FIXME: This needs to be an auto-reversible write. */ + pci_mmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL); + + /* Get I/O BAR location. */ + tmp = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_2) & + PCI_BASE_ADDRESS_IO_MASK; + /* Truncate to reachable range. + * FIXME: Check if the I/O BAR is actually reachable. + * This is an arch specific check. + */ + mv_iobar = tmp & 0xffff; + msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar); + + buses_supported = CHIP_BUSTYPE_PARALLEL; + + /* 512 kByte with two 8-bit latches, and + * 4 MByte with additional 3-bit latch. */ + max_rom_decode.parallel = 4 * 1024 * 1024; + + return 0; + +error_out: + pci_cleanup(pacc); + release_io_perms(); + return 1; +} + +int satamv_shutdown(void) +{ + physunmap(mv_bar, 0x20000); + pci_cleanup(pacc); + release_io_perms(); + return 0; +} + +/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function. + * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O). + * This code only supports indirect accesses for now. + */ + +/* Indirect access to via the I/O BAR1. */ +static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr) +{ + /* 0x80000000 selects BAR2 for remapping. */ + OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); + OUTB(val, mv_iobar + 0x80 + (addr & 0x3)); +} + +/* Indirect access to via the I/O BAR1. */ +static uint8_t satamv_indirect_chip_readb(const chipaddr addr) +{ + /* 0x80000000 selects BAR2 for remapping. */ + OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); + return INB(mv_iobar + 0x80 + (addr & 0x3)); +} + +/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ +void satamv_chip_writeb(uint8_t val, chipaddr addr) +{ + satamv_indirect_chip_writeb(val, addr); +} + +/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ +uint8_t satamv_chip_readb(const chipaddr addr) +{ + return satamv_indirect_chip_readb(addr); +} Index: flashrom-marvell/Makefile =================================================================== --- flashrom-marvell/Makefile (Revision 1257) +++ flashrom-marvell/Makefile (Arbeitskopie) @@ -155,6 +155,9 @@ # Disable Dediprog SF100 until support is complete and tested. CONFIG_DEDIPROG ?= no +# Always enable Marvell SATA controllers for now. +CONFIG_SATAMV ?= yes + # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no @@ -283,6 +286,12 @@ PROGRAMMER_OBJS += dediprog.o endif +ifeq ($(CONFIG_SATAMV), yes) +FEATURE_CFLAGS += -D'CONFIG_SATAMV=1' +PROGRAMMER_OBJS += satamv.o +NEED_PCI := yes +endif + ifeq ($(NEED_SERIAL), yes) LIB_OBJS += serial.o endif Index: flashrom-marvell/print_wiki.c =================================================================== --- flashrom-marvell/print_wiki.c (Revision 1257) +++ flashrom-marvell/print_wiki.c (Arbeitskopie) @@ -302,6 +302,9 @@ #if CONFIG_OGP_SPI == 1 print_supported_pcidevs_wiki(ogp_spi); #endif +#if CONFIG_SATAMV == 1 + print_supported_pcidevs_wiki(satas_mv); +#endif printf("\n|}\n"); } Index: flashrom-marvell/flashrom.c =================================================================== --- flashrom-marvell/flashrom.c (Revision 1257) +++ flashrom-marvell/flashrom.c (Arbeitskopie) @@ -52,7 +52,7 @@ * if more than one of them is selected. If only one is selected, it is clear * that the user wants that one to become the default. */ -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI > 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one. #endif enum programmer programmer = @@ -99,6 +99,9 @@ #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI #endif +#if CONFIG_SATAMV == 1 + PROGRAMMER_SATAMV +#endif ; #endif @@ -461,6 +464,25 @@ }, #endif +#if CONFIG_SATAMV == 1 + { + .name = "satamv", + .init = satamv_init, + .shutdown = satamv_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = satamv_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = satamv_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + {}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; Index: flashrom-marvell/programmer.h =================================================================== --- flashrom-marvell/programmer.h (Revision 1257) +++ flashrom-marvell/programmer.h (Arbeitskopie) @@ -79,6 +79,9 @@ #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI, #endif +#if CONFIG_SATAMV == 1 + PROGRAMMER_SATAMV, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -415,6 +418,15 @@ extern const struct pcidev_status ogp_spi[]; #endif +/* satamv.c */ +#if CONFIG_SATAMV == 1 +int satamv_init(void); +int satamv_shutdown(void); +void satamv_chip_writeb(uint8_t val, chipaddr addr); +uint8_t satamv_chip_readb(const chipaddr addr); +extern const struct pcidev_status satas_mv[]; +#endif + /* satasii.c */ #if CONFIG_SATASII == 1 int satasii_init(void); Index: flashrom-marvell/print.c =================================================================== --- flashrom-marvell/print.c (Revision 1257) +++ flashrom-marvell/print.c (Arbeitskopie) @@ -317,6 +317,11 @@ programmer_table[PROGRAMMER_OGP_SPI].name); print_supported_pcidevs(ogp_spi); #endif +#if CONFIG_SATAMV == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_SATAMV].name); + print_supported_pcidevs(satas_mv); +#endif } #if CONFIG_INTERNAL == 1 -- http://www.hailfinger.org/

3 5

[commit] r1258 - trunk
by repository service 04 Feb '11

04 Feb '11

Author: hailfinger Date: Fri Feb 4 22:37:59 2011 New Revision: 1258 URL: http://flashrom.org/trac/flashrom/changeset/1258 Log: Support for Angelbird Wings PCIe SSD (solid-state drive). It uses a Marvell 88SX7042 SATA controller internally which has access to a separate flash chip hosting the option ROM. Thanks to Angelbird Ltd for sponsoring development of this driver! I expect the code to work for that SATA controller even if it is not part of the Angelbird SSD. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Added: trunk/satamv.c Modified: trunk/Makefile trunk/flashrom.c trunk/print.c trunk/print_wiki.c trunk/programmer.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri Jan 28 10:00:15 2011 (r1257) +++ trunk/Makefile Fri Feb 4 22:37:59 2011 (r1258) @@ -155,6 +155,9 @@ # Disable Dediprog SF100 until support is complete and tested. CONFIG_DEDIPROG ?= no +# Always enable Marvell SATA controllers for now. +CONFIG_SATAMV ?= yes + # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no @@ -283,6 +286,12 @@ PROGRAMMER_OBJS += dediprog.o endif +ifeq ($(CONFIG_SATAMV), yes) +FEATURE_CFLAGS += -D'CONFIG_SATAMV=1' +PROGRAMMER_OBJS += satamv.o +NEED_PCI := yes +endif + ifeq ($(NEED_SERIAL), yes) LIB_OBJS += serial.o endif Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Fri Jan 28 10:00:15 2011 (r1257) +++ trunk/flashrom.c Fri Feb 4 22:37:59 2011 (r1258) @@ -52,7 +52,7 @@ * if more than one of them is selected. If only one is selected, it is clear * that the user wants that one to become the default. */ -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI > 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one. #endif enum programmer programmer = @@ -99,6 +99,9 @@ #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI #endif +#if CONFIG_SATAMV == 1 + PROGRAMMER_SATAMV +#endif ; #endif @@ -461,6 +464,25 @@ }, #endif +#if CONFIG_SATAMV == 1 + { + .name = "satamv", + .init = satamv_init, + .shutdown = satamv_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = satamv_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = satamv_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + {}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; Modified: trunk/print.c ============================================================================== --- trunk/print.c Fri Jan 28 10:00:15 2011 (r1257) +++ trunk/print.c Fri Feb 4 22:37:59 2011 (r1258) @@ -317,6 +317,11 @@ programmer_table[PROGRAMMER_OGP_SPI].name); print_supported_pcidevs(ogp_spi); #endif +#if CONFIG_SATAMV == 1 + printf("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_SATAMV].name); + print_supported_pcidevs(satas_mv); +#endif } #if CONFIG_INTERNAL == 1 Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Fri Jan 28 10:00:15 2011 (r1257) +++ trunk/print_wiki.c Fri Feb 4 22:37:59 2011 (r1258) @@ -302,6 +302,9 @@ #if CONFIG_OGP_SPI == 1 print_supported_pcidevs_wiki(ogp_spi); #endif +#if CONFIG_SATAMV == 1 + print_supported_pcidevs_wiki(satas_mv); +#endif printf("\n|}\n"); } Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Fri Jan 28 10:00:15 2011 (r1257) +++ trunk/programmer.h Fri Feb 4 22:37:59 2011 (r1258) @@ -79,6 +79,9 @@ #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI, #endif +#if CONFIG_SATAMV == 1 + PROGRAMMER_SATAMV, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -415,6 +418,15 @@ extern const struct pcidev_status ogp_spi[]; #endif +/* satamv.c */ +#if CONFIG_SATAMV == 1 +int satamv_init(void); +int satamv_shutdown(void); +void satamv_chip_writeb(uint8_t val, chipaddr addr); +uint8_t satamv_chip_readb(const chipaddr addr); +extern const struct pcidev_status satas_mv[]; +#endif + /* satasii.c */ #if CONFIG_SATASII == 1 int satasii_init(void); Added: trunk/satamv.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/satamv.c Fri Feb 4 22:37:59 2011 (r1258) @@ -0,0 +1,183 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010,2011 Carl-Daniel Hailfinger + * Written by Carl-Daniel Hailfinger for Angelbird Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Datasheets are not public (yet?) */ + +#include <stdlib.h> +#include "flash.h" +#include "programmer.h" + +uint8_t *mv_bar; +uint16_t mv_iobar; + +const struct pcidev_status satas_mv[] = { + /* 88SX6041 and 88SX6042 are the same according to the datasheet. */ + {0x11ab, 0x7042, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II"}, + + {}, +}; + +#define NVRAM_PARAM 0x1045c +#define FLASH_PARAM 0x1046c +#define EXPANSION_ROM_BAR_CONTROL 0x00d2c +#define PCI_BAR2_CONTROL 0x00c08 +#define GPIO_PORT_CONTROL 0x104f0 + +/* + * Random notes: + * FCE# Flash Chip Enable + * FWE# Flash Write Enable + * FOE# Flash Output Enable + * FALE[1:0] Flash Address Latch Enable + * FAD[7:0] Flash Multiplexed Address/Data Bus + * FA[2:0] Flash Address Low + * + * GPIO[15,2] GPIO Port Mode + * GPIO[4:3] Flash Size + * + * 0xd2c Expansion ROM BAR Control + * 0xc08 PCI BAR2 (Flash/NVRAM) Control + * 0x1046c Flash Parameters + */ +int satamv_init(void) +{ + uintptr_t addr; + uint32_t tmp; + + get_io_perms(); + + /* BAR0 has all internal registers memory mapped. */ + /* No need to check for errors, pcidev_init() will not return in case + * of errors. + */ + addr = pcidev_init(0x11ab, PCI_BASE_ADDRESS_0, satas_mv); + + mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000); + if (mv_bar == ERROR_PTR) + goto error_out; + + tmp = pci_mmio_readl(mv_bar + FLASH_PARAM); + msg_pspew("Flash Parameters:\n"); + msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7); + msg_pspew("Acc2First=0x%01x\n", (tmp >> 3) & 0xf); + msg_pspew("Acc2Next=0x%01x\n", (tmp >> 7) & 0xf); + msg_pspew("ALE2Wr=0x%01x\n", (tmp >> 11) & 0x7); + msg_pspew("WrLow=0x%01x\n", (tmp >> 14) & 0x7); + msg_pspew("WrHigh=0x%01x\n", (tmp >> 17) & 0x7); + msg_pspew("Reserved[21:20]=0x%01x\n", (tmp >> 20) & 0x3); + msg_pspew("TurnOffExt=0x%01x\n", (tmp >> 22) & 0x1); + msg_pspew("Acc2FirstExt=0x%01x\n", (tmp >> 23) & 0x1); + msg_pspew("Acc2NextExt=0x%01x\n", (tmp >> 24) & 0x1); + msg_pspew("ALE2WrExt=0x%01x\n", (tmp >> 25) & 0x1); + msg_pspew("WrLowExt=0x%01x\n", (tmp >> 26) & 0x1); + msg_pspew("WrHighExt=0x%01x\n", (tmp >> 27) & 0x1); + msg_pspew("Reserved[31:28]=0x%01x\n", (tmp >> 28) & 0xf); + + tmp = pci_mmio_readl(mv_bar + EXPANSION_ROM_BAR_CONTROL); + msg_pspew("Expansion ROM BAR Control:\n"); + msg_pspew("ExpROMSz=0x%01x\n", (tmp >> 19) & 0x7); + + /* Enable BAR2 mapping to flash */ + tmp = pci_mmio_readl(mv_bar + PCI_BAR2_CONTROL); + msg_pspew("PCI BAR2 (Flash/NVRAM) Control:\n"); + msg_pspew("Bar2En=0x%01x\n", (tmp >> 0) & 0x1); + msg_pspew("BAR2TransAttr=0x%01x\n", (tmp >> 1) & 0x1f); + msg_pspew("BAR2Sz=0x%01x\n", (tmp >> 19) & 0x7); + tmp &= 0xffffffc0; + tmp |= 0x0000001f; + /* FIXME: This needs to be an auto-reversible write. */ + pci_mmio_writel(tmp, mv_bar + PCI_BAR2_CONTROL); + + /* Enable flash: GPIO Port Control Register 0x104f0 */ + tmp = pci_mmio_readl(mv_bar + GPIO_PORT_CONTROL); + msg_pspew("GPIOPortMode=0x%01x\n", (tmp >> 0) & 0x3); + if (((tmp >> 0) & 0x3) != 0x2) + msg_pinfo("Warning! Either the straps are incorrect or you " + "have no flash or someone overwrote the strap " + "values!\n"); + tmp &= 0xfffffffc; + tmp |= 0x2; + /* FIXME: This needs to be an auto-reversible write. */ + pci_mmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL); + + /* Get I/O BAR location. */ + tmp = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_2) & + PCI_BASE_ADDRESS_IO_MASK; + /* Truncate to reachable range. + * FIXME: Check if the I/O BAR is actually reachable. + * This is an arch specific check. + */ + mv_iobar = tmp & 0xffff; + msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar); + + buses_supported = CHIP_BUSTYPE_PARALLEL; + + /* 512 kByte with two 8-bit latches, and + * 4 MByte with additional 3-bit latch. */ + max_rom_decode.parallel = 4 * 1024 * 1024; + + return 0; + +error_out: + pci_cleanup(pacc); + release_io_perms(); + return 1; +} + +int satamv_shutdown(void) +{ + physunmap(mv_bar, 0x20000); + pci_cleanup(pacc); + release_io_perms(); + return 0; +} + +/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function. + * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O). + * This code only supports indirect accesses for now. + */ + +/* Indirect access to via the I/O BAR1. */ +static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr) +{ + /* 0x80000000 selects BAR2 for remapping. */ + OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); + OUTB(val, mv_iobar + 0x80 + (addr & 0x3)); +} + +/* Indirect access to via the I/O BAR1. */ +static uint8_t satamv_indirect_chip_readb(const chipaddr addr) +{ + /* 0x80000000 selects BAR2 for remapping. */ + OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); + return INB(mv_iobar + 0x80 + (addr & 0x3)); +} + +/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ +void satamv_chip_writeb(uint8_t val, chipaddr addr) +{ + satamv_indirect_chip_writeb(val, addr); +} + +/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ +uint8_t satamv_chip_readb(const chipaddr addr) +{ + return satamv_indirect_chip_readb(addr); +}

1 0

[PATCH 1/1] Board-enable for GA-K8N51GMF
by Michael Karcher 04 Feb '11

04 Feb '11

(VERIFIED to contain the right patch) Gigabyte is not really helpful with their PCI IDs for us, the subsystem IDs used just mean "gigabyte northbridge" and "gigabyte southbridge". We should investigate whether autodetection of this board is causing interference with other boards. real version 2: Extend list of PCI IDs for nvidia southbridges. flashrom -V: http://paste.flashrom.org/view.php?id=326 lspic: http://paste.flashrom.org/view.php?id=328 superiotool: http://paste.flashrom.org/view.php?id=329 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 5 ++++- print.c | 1 + 2 files changed, 5 insertions(+), 1 deletions(-) diff --git a/board_enable.c b/board_enable.c index 5776bf5..75adc9e 100644 --- a/board_enable.c +++ b/board_enable.c @@ -866,6 +866,7 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) case 0x00E0: /* CK8 */ break; case 0x0260: /* MCP51 */ + case 0x0261: /* MCP51 */ case 0x0364: /* MCP55 */ /* find SMBus controller on *this* southbridge */ /* The infamous Tyan S2915-E has two south bridges; they are @@ -1026,7 +1027,8 @@ static int nvidia_mcp_gpio31_raise(void) /* * Suited for: - * - GIGABYTE GA-K8N51GMF-9 + * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51 + * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51 */ static int nvidia_mcp_gpio3b_raise(void) { @@ -1938,6 +1940,7 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, + {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable}, diff --git a/print.c b/print.c index 7ba2801..01a32c6 100644 --- a/print.c +++ b/print.c @@ -476,6 +476,7 @@ const struct board_info boards_known[] = { B("GIGABYTE", "GA-EP35-DS3L", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-EX58-UD4P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL), B("GIGABYTE", "GA-K8N-SLI", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1928", NULL), + B("GIGABYTE", "GA-K8N51GMF", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1950", NULL), B("GIGABYTE", "GA-K8N51GMF-9", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1939", NULL), B("GIGABYTE", "GA-M57SLI-S4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2287", NULL), B("GIGABYTE", "GA-M61P-S3", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2434", NULL), -- 1.7.2.3

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[PATCH 1/1] Board-enable for GA-K8N51GMF
by Michael Karcher 04 Feb '11

04 Feb '11

(this time *really* the updated patch!) Gigabyte is not really helpful with their PCI IDs for us, the subsystem IDs used just mean "gigabyte northbridge" and "gigabyte southbridge". We should investigate whether autodetection of this board is causing interference with other boards. version 2: Extend list of PCI IDs for nvidia southbridges. flashrom -V: http://paste.flashrom.org/view.php?id=326 lspic: http://paste.flashrom.org/view.php?id=328 superiotool: http://paste.flashrom.org/view.php?id=329 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 4 +++- print.c | 1 + 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/board_enable.c b/board_enable.c index 5776bf5..4b9c515 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1026,7 +1026,8 @@ static int nvidia_mcp_gpio31_raise(void) /* * Suited for: - * - GIGABYTE GA-K8N51GMF-9 + * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51 + * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51 */ static int nvidia_mcp_gpio3b_raise(void) { @@ -1938,6 +1939,7 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, + {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable}, diff --git a/print.c b/print.c index 7ba2801..01a32c6 100644 --- a/print.c +++ b/print.c @@ -476,6 +476,7 @@ const struct board_info boards_known[] = { B("GIGABYTE", "GA-EP35-DS3L", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-EX58-UD4P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL), B("GIGABYTE", "GA-K8N-SLI", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1928", NULL), + B("GIGABYTE", "GA-K8N51GMF", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1950", NULL), B("GIGABYTE", "GA-K8N51GMF-9", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1939", NULL), B("GIGABYTE", "GA-M57SLI-S4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2287", NULL), B("GIGABYTE", "GA-M61P-S3", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2434", NULL), -- 1.7.2.3

1 0

CR-48 help
by Brian Davis 03 Feb '11

03 Feb '11

Do you have any experience with the cr-48 and hexxeh's script?

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flashrom February 2011