flashrom September 2010

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68 participants
216 discussions

[Patch] Reduce usage of w836xx_memw
by David Borg 14 Sep '10

14 Sep '10

Patch reduces usage of w836xx_memw functions and board enables, which would become redundant after "[PATCH] W83697xx superio flash enable" is hooked up to generic superio detection. Signed-off-by: David Borg <borg.db(a)gmail.com> Regards, David

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[commit] r1163 - trunk
by repository service 14 Sep '10

14 Sep '10

Author: uwe Date: Tue Sep 14 01:00:57 2010 New Revision: 1163 URL: http://flashrom.org/trac/flashrom/changeset/1163 Log: Add support for the abit BM6 board. Signed-off-by: Tim ter Laak <timl(a)scintilla.utwente.nl> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Mon Sep 13 21:59:28 2010 (r1162) +++ trunk/board_enable.c Tue Sep 14 01:00:57 2010 (r1163) @@ -1155,6 +1155,15 @@ /* * Suited for: + * - abit BM6 + */ +static int intel_piix4_gpo26_lower(void) +{ + return intel_piix4_gpo_set(26, 0); +} + +/* + * Suited for: * - Intel SE440BX-2 */ static int intel_piix4_gpo27_lower(void) @@ -1828,6 +1837,7 @@ /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ #if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, + {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower}, {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, "abit", "IC7", 0, NT, intel_ich_gpio23_raise}, {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Mon Sep 13 21:59:28 2010 (r1162) +++ trunk/print.c Tue Sep 14 01:00:57 2010 (r1163) @@ -283,6 +283,7 @@ B("A-Trend", "ATC-6220", 1, "http://www.motherboard.cz/mb/atrend/atc6220.htm", NULL), B("abit", "AN-M2", 1, "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), B("abit", "AX8", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), + B("abit", "BM6", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), B("abit", "Fatal1ty F-I90HD", 1, "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), B("abit", "IC7", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), B("abit", "IP35", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=LG…", NULL),

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Re: [coreboot] flashrom patch: add support for Abit AB-BM6 board
by Carl-Daniel Hailfinger 14 Sep '10

14 Sep '10

Hi Tim, it seems your flashrom patch from exactly two years ago slipped through the cracks until now. I'm very sorry about that. Do you still own the board? If yes, could you please run download latest flashrom (at least 0.9.2, preferably latest svn) and provide the output of the following commands (as root): flashrom -V superiotool -deV flashrom supports DMI matching since a few months, so it may be possible to identify your board that way. And with superiotool output, we could perhaps improve matching a bit more. You already provided full lspci -nnvvxx output at http://marc.info/?l=linuxbios&m=122276697617977&w=2 so I'm not going to request that again. (I couldn't link to the coreboot.org mailing list archives because that message is corrupt). On 03.09.2008 11:42, Tim ter Laak wrote: > This patch adds support for the Abit AB-BM6 mainboard to flashrom. > > The biggest part is a generic function to lower a GPIO line on the > PIIX4E southbridge, copied and adapted from its ich_gpio_raise() > counterpart (mostly lower instead of raise, followed names from the > PIIX4E datasheet). The board specific function then uses this to lower > GPO 26. > > Signed-off-by: Tim ter Laak <timl(a)scintilla.utwente.nl> > > +/** > + * Suited for Abit AB-BM6. > + */ > +static int piix4_gpio26_lower(const char *name) > +{ > + return piix4_gpio_lower(name, 0x8086, 0x7113, 0x40, 0x34, 0xffc0, 26); With current flashrom, the line above would look like this: return intel_piix4_gpo_set(26, 0); > +} > + > + > + > +/** > * Suited for Acorp 6A815EPD. > */ > static int board_acorp_6a815epd(const char *name) > @@ -672,6 +724,8 @@ > NULL, NULL, "GIGABYTE GA-7VT600", board_biostar_p4m80_m4}, > {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, > NULL, NULL, "MSI K8T Neo2", w83627thf_gpio4_4_raise_2e}, > + {0x8086, 0x7190, 0x0000, 0x0000, 0x8086, 0x7110, 0x0000, 0x0000, > + "abit", "ab-bm6", "Abit AB-BM6", piix4_gpio26_lower}, > {0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */ > }; If DMI is useful on your board, we could try to match the DMI strings and avoid the -m abit:ab-bm6 parameter for flashrom. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH] support for MX251635E
by Stephan GUILLOUX 13 Sep '10

13 Sep '10

Hello, Below, a patch to allow MX25L1635E support, as discussed with Carldani. It is also available in attachment. This one is working fine on our system, with flashrom 0.9.2 Sorry for the patch, but I do not have svn anymore. I had to use a standard diff -c. Make good use of it;-) Stephan. Signed-off-by: Stephan Guilloux<stephan.guilloux(a)free.fr> --- ./flashrom-0.9.2.org/flashchips.h 2010-04-20 21:34:31.000000000 +0200 +++ ./flashrom-0.9.2.new/flashchips.h 2010-09-03 09:37:39.386013000 +0200 @@ -284,7 +284,8 @@ #define MX_25L6405 0x2017 /* MX25L3205{,D} */ #define MX_25L12805 0x2018 /* MX25L12805 */ #define MX_25L1635D 0x2415 +#define MX_25L1635E 0x2515 /* MX25L1635{E} */ #define MX_25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ #define MX_29F001B 0x19 #define MX_29F001T 0x18 --- ./flashrom-0.9.2.org/flashchips.c 2010-04-20 21:34:31.000000000 +0200 +++ ./flashrom-0.9.2.new/flashchips.c 2010-09-03 09:38:44.637466000 +0200 @@ -2775,6 +2775,37 @@ { .vendor = "Macronix", + .name = "MX25L1635E", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = MX_ID, + .model_id = MX_25L1635E, + .total_size = 2048, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Macronix", .name = "MX25L3205", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = MX_ID,

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[commit] r1162 - trunk
by repository service 13 Sep '10

13 Sep '10

Author: uwe Date: Mon Sep 13 21:59:28 2010 New Revision: 1162 URL: http://flashrom.org/trac/flashrom/changeset/1162 Log: Add support for the Macronix MX251635E chip. Signed-off-by: Stephan Guilloux <stephan.guilloux(a)free.fr> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Mon Sep 13 21:39:25 2010 (r1161) +++ trunk/flashchips.c Mon Sep 13 21:59:28 2010 (r1162) @@ -3623,6 +3623,39 @@ { .vendor = "Macronix", + .name = "MX25L1635E", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = MX_ID, + .model_id = MX_25L1635E, + .total_size = 2048, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Macronix", .name = "MX25L3205", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = MX_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Mon Sep 13 21:39:25 2010 (r1161) +++ trunk/flashchips.h Mon Sep 13 21:59:28 2010 (r1162) @@ -316,6 +316,7 @@ #define MX_25L6405 0x2017 /* MX25L3205{,D} */ #define MX_25L12805 0x2018 /* MX25L12805 */ #define MX_25L1635D 0x2415 +#define MX_25L1635E 0x2515 /* MX25L1635{E} */ #define MX_25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ #define MX_29F001B 0x19 #define MX_29F001T 0x18

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ASUS P4SC-E Board Enable / IT8707F support
by Mattias Mattsson 13 Sep '10

13 Sep '10

Hi, The attached patch adds board enable for the ASUS P4SC-E board. It does this by setting bits 3..2 of register 0x24 on the super i/o chip, while keeping bit 3 of register 0x23 set while manipulating the first register. I have no idea what this actually means since no public datasheet is available, but this is how the vendor BIOS does it. Tested on a P4SC-E with SST 39SF020A flash. Probe, read, erase, write all work. Matching on NB/SB. lspci/superio output: http://www.flashrom.org/pipermail/flashrom/2010-July/004090.html The ITE IT8707F chip seems to have been manufactured exclusively for ASUS: http://lists.lm-sensors.org/pipermail/lm-sensors/2002-October/001260.html In the past (before it's release) the IT8707F was listed on the ITE website: http://web.archive.org/web/20000510121435/http://www.ite.com.tw/productInfo… By looking through some ASUS manuals I have found that at least 17 ASUS boards is using this chip: P4S133/-VM P4S333/-FX/-M/-VF/-VM P4S533/-E/-VM P4SC/-E/-EA ("Terminator P4" barebone series) P4SDR-VM P4SE/U2 P4SGL-VM The vendor BIOS of these boards all use the same super i/o flash enable code described above. The following boards additionally clears bit 6 of IDX F4, LDN 7 in the flash enabling routine: P4S133, P4S333, P4S533, P4S533-E, P4SE, P4SE/U2. (Not included in this patch since I don't own any of these.) Many thanks to Reinder de Haan for help with reverse engineering this! Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com>

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[commit] r1161 - trunk
by repository service 13 Sep '10

13 Sep '10

Author: mhm Date: Mon Sep 13 21:39:25 2010 New Revision: 1161 URL: http://flashrom.org/trac/flashrom/changeset/1161 Log: Add board enable for ASUS P4SC-E. I does this by setting bits 3..2 of register 0x24 on the ITE IT8707F, while keeping bit 3 of register 0x23 set while manipulating the first register. AFAIK, there is no public datasheet available for this super i/o chip, but the above is how the vendor BIOS does it. Also, registers 0x23 and 0x24 seem to have the same meaning as on the ITE IT8710F. Matching on NB/SB. Tested on a P4SC-E with SST 39SF020A flash. Probe, read, erase, write all work. lspci/superio output: http://www.flashrom.org/pipermail/flashrom/2010-July/004090.html flashrom output: http://www.flashrom.org/pipermail/flashrom/2010-August/004566.html Many thanks to Reinder de Haan for help with reverse engineering this! Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Mon Sep 13 20:22:36 2010 (r1160) +++ trunk/board_enable.c Mon Sep 13 21:39:25 2010 (r1161) @@ -498,6 +498,48 @@ return ret; } +/* + * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS. + * It uses the Winbond command sequence to enter extended configuration + * mode and the ITE sequence to exit. + * + * Registers seems similar to the ones on ITE IT8710F. + */ +static int it8707f_write_enable(uint8_t port) +{ + uint8_t tmp; + + w836xx_ext_enter(port); + + /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */ + tmp = sio_read(port, 0x23); + tmp |= (1 << 3); + sio_write(port, 0x23, tmp); + + /* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */ + tmp = sio_read(port, 0x24); + tmp |= (1 << 2) | (1 << 3); + sio_write(port, 0x24, tmp); + + /* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */ + tmp = sio_read(port, 0x23); + tmp &= ~(1 << 3); + sio_write(port, 0x23, tmp); + + exit_conf_mode_ite(port); + + return 0; +} + +/* + * Suited for: + * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F + */ +static int it8707f_write_enable_2e(void) +{ + return it8707f_write_enable(0x2e); +} + static int pc87360_gpio_set(uint8_t gpio, int raise) { static const int bankbase[] = {0, 4, 8, 10, 12}; @@ -1818,6 +1860,7 @@ {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e}, {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Mon Sep 13 20:22:36 2010 (r1160) +++ trunk/print.c Mon Sep 13 21:39:25 2010 (r1161) @@ -363,6 +363,7 @@ B("ASUS", "P4C800-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=cFuVCr9bXXCckmcK", NULL), B("ASUS", "P4P800", 1, "http://www.asus.com/product.aspx?P_ID=DYt1Et9MlBChqzLb", NULL), B("ASUS", "P4P800-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=INIJUvLlif7LHp3g", NULL), + B("ASUS", "P4SC-E", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock478/p4sc-e/", "Part of ASUS Terminator P4 533 barebone system"), B("ASUS", "P4SD-LA", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00022505", NULL), B("ASUS", "P4S800-MX", 1, "http://www.asus.com/product.aspx?P_ID=Bb57zoJhmO1Qkcrh", NULL), B("ASUS", "P5A", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock7/ali/p5a/", NULL),

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ST M25PX32 and M25PX64 flash chip support
by Jason Shriver 13 Sep '10

13 Sep '10

Add support for ST M25PX32 and M25PX64 flash chips. Probe, read, erase and write have been tested and all are functional. Signed-off-by: Jason Shriver <j.shriver(a)f5.com>

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[PATCH] Fix a bitmask in it87spi_probe.
by Joshua Roys 13 Sep '10

13 Sep '10

Hello, I think the first shift should be a 0 since the one below it is 1, then 2, then 3, etc. Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Thanks, Josh

2 1

[PATCH] Board enable for MSI MS-6163 rev:2 (MS-6163 Pro) (try 2)
by Mattias Mattsson 13 Sep '10

13 Sep '10

Hi, This patch adds a board enable for MS-6163 Pro (MS-6163 rev:2) http://www.msi.com/index.php?func=proddesc&prod_no=340 Matching on NB/SB. Probe, read, erase and write all work. lspci/superiotool output: http://www.flashrom.org/pipermail/flashrom/2010-August/004461.html Previous version of this patch: http://www.flashrom.org/pipermail/flashrom/2010-August/004463.html I believe that this board enable also works for MSI BX Master (MS-6163 rev:3) and perhaps also for MSI MS-6163FC (MS-6163 rev:1) but these boards have not been tested. Test logs for MS-6163 (rev:2) attached. Thanks, -mattias

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flashrom September 2010