flashrom September 2010

flashrom@flashrom.org

68 participants
216 discussions

rayer_spi programmer support
by Chris Enrique 14 Sep '10

14 Sep '10

Hello, i was just wondering if flashrom supports the SPI parallel programmer mentioned on this website: http://rayer.ic.cz/elektro/spipgm.htm The author says it does as he provided his sourcecode to your project. but if i use the command : flashrom -p rayer_spi ... it says unknown programmer. can somebody give me some informations on this issue? thank you chris

2 2

[PATCH 1/1] Define dmidecode path at a build stage
by Peter Lemenkov 14 Sep '10

14 Sep '10

This helps in case then user doesn't have dmidecode in his PATH. For example, if user elevates his privileges with sudo, then he may not inherit some superuser's environmental variables ($PATH, contaning additional directories - /sbin, /usr/sbin and similar). In case of failure to determine full path to dmidecode it just fallbacks to the default value. Tested only on Linux. Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- Makefile | 5 ++++- dmi.c | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index e83fc0b..7919e10 100644 --- a/Makefile +++ b/Makefile @@ -169,6 +169,9 @@ CONFIG_DEDIPROG ?= no # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no +# Try to detect full path for dmidecode +CONFIG_DMIDECODE_PATH ?= $(shell LC_ALL=C type -p dmidecode 2>/dev/null || echo "dmidecode") + ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o @@ -323,7 +326,7 @@ $(PROGRAM)$(EXEC_SUFFIX): $(OBJS) TAROPTIONS = $(shell LC_ALL=C tar --version|grep -q GNU && echo "--owner=root --group=root") %.o: %.c .features - $(CC) -MMD $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SVNDEF) -o $@ -c $< + $(CC) -MMD $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SVNDEF) -DCONFIG_DMIDECODE_PATH=\"$(CONFIG_DMIDECODE_PATH)\" -o $@ -c $< # Make sure to add all names of generated binaries here. # This includes all frontends and libflashrom. diff --git a/dmi.c b/dmi.c index f18907f..d483acb 100644 --- a/dmi.c +++ b/dmi.c @@ -55,7 +55,7 @@ static const char *dmidecode_names[] = { }; #define DMI_COMMAND_LEN_MAX 260 -static const char *dmidecode_command = "dmidecode"; +static const char *dmidecode_command = CONFIG_DMIDECODE_PATH; static char *dmistrings[ARRAY_SIZE(dmidecode_names)]; -- 1.7.2.3

2 2

Abit VA6 / Atmel AT49F002NT
by Mattias Mattsson 14 Sep '10

14 Sep '10

Hi, I have tested flashrom r1138 on an Abit VA6 with Atmel AT49F002NT flash. Probe, read, erase, write all work together with this patch: http://www.coreboot.org/pipermail/flashrom/2010-August/004439.html lspci crashes with the -xxx option on this board (the lspci manpage mentions this could happen) so output is with -x only. Logs attached. Thanks -mattias

4 4

[PATCH] Winbond chip id fix-up (ver 3)
by Mattias Mattsson 14 Sep '10

14 Sep '10

New version. List all chip variants in the .name strings in flashchips.c Also have two identical entries for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012 with different probe functions in flashchips.c as sometimes (for newer revisions of these chips?) the standard jedec probe seems to work. Eg see test report here: http://patchwork.coreboot.org/patch/1476/ Rename constants W_nnnn -> WINBOND_Wnnnn W_25nnn -> WINBOND_NEX_W25nnn Kill incorrect ASD chip and vendor id. Group Winbond SPI and Parallell chips separately (they have different vendor ids). Change constant names to the "canonical" chip name for the following ids: W_29C020C (0x45) -> WINBOND_W29C020 (Same as W29C020C, W29C022 and ASD AE29F2008) W_29C040P (0x46) -> WINBOND_W29C040 ("P" is for package type [32-pin PLCC], irrelevant) W_29C011 + W_29EE011 (0xC1) -> WINBOND_W29C010M (Same as W29C011A, W29EE011, W29EE012, and ASD AE29F1008) Also add ids for the following Winbond chips: W25Q40 W25Q128 W19B160BB W19B160BT W19B320SB/W19L320SB W19B320ST/W19L320ST W19B322MB W19B322MT W19B323MB W19B323MT W19B324MB W19B324MT W29C512A/W29EE512 W39L010 W39L040A W39L512 W49F002/W49F002B Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com>

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[PATCH] Intel chip id fix-up (ver 2)
by Mattias Mattsson 14 Sep '10

14 Sep '10

This is a new version of an earlier patch. Strip package prefix in constant names (everything before "28F"). Prefix every constant name with INTEL_ Sort intel chip constants by id. Rename the following constants to their "canonical" name: P28F400BT (0x70) -> INTEL_28F400T (28F400BV/BX/CE/CV-T) P28F400BB (0x71) -> INTEL_28F400B (28F400BV/BX/CE/CV-B) P28F004BT (0x78) -> INTEL_28F004T (28F004B5/BE/BV/BX-T) P28F004BB (0x79) -> INTEL_28F004B (28F004B5/BE/BV/BX-B) E_28F008S5 (0xA6) -> INTEL_28F008S3 (28F008S3/S5/SC) E_28F004S5 (0xA7) -> INTEL_28F004S3 (28F008S3/S5/SC) P28F001BXT (0x94) -> INTEL_28F001T (28F001BN/BX-T) P28F001BXB (0x95) -> INTEL_28F001B (28F001BN/BX-B) E_28F016S5 (0xAA) -> INTEL_28F016S3 (28F016S3/S5/SC) Also add chip ids for the following chips: 28F320J5 28F640J5 28F320J3 28F640J3 28F128J3 28F256J3 28F200BL/BV/BX/CV-T 28F200BL/BV/BX/CV-B 28F002BL/BV/BX-B 28F008BE/BV-T 28F008BE/BV-B 28F800B5/BV/CE/CV-T 28F800B5/BV/CE/CV-B 28F016SA/SV 28F008SA 28F008S3/S5/SC 28F008S3/S5/SC 28F016XS 28F010 28F512 28F256A 28F020 28F016B3-T 28F016B3-B 28F008B3-T 28F008B3-B 28F004B3-T 28F004B3-B Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com>

1 0

[PATCH] Winbond chip id fix-up (ver 2)
by Mattias Mattsson 14 Sep '10

14 Sep '10

Hi, This is an updated version of an earlier patch. Now additionally changes all constants: W_nnnn -> WINBOND_Wnnnn W_25nnn -> WINBOND_NEX_W25nnn Kill incorrect ASD chip and vendor id. Group Winbond SPI and Parallell chips separately (they have different vendor ids). Change constant names to the "canonical" chip name for the following ids: W_29C020C (0x45) -> WINBOND_W29C020 (Same as W29C020C, W29C022 and ASD AE29F2008) W_29C040P (0x46) -> WINBOND_W29C040 ("P" is for package type [32-pin PLCC], irrelevant) W_29C011 + W_29EE011 (0xC1) -> WINBOND_W29C010M (Same as W29C011A, W29EE011, W29EE012, and ASD AE29F1008) Also add ids for the following Winbond chips: W25Q40 W25Q128 W19B160BB W19B160BT W19B320SB/W19L320SB W19B320ST/W19L320ST W19B322MB W19B322MT W19B323MB W19B323MT W19B324MB W19B324MT W29C512A/W29EE512 W39L010 W39L040A W39L512 W49F002/W49F002B Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com>

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[PATCH] Nvidia MCP SPI speedup
by Carl-Daniel Hailfinger 14 Sep '10

14 Sep '10

Use caching for Nvidia MCP SPI GPIO accesses. Reduce clock delay to zero. Should result in a 2x speedup, maybe more. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-bitbang_spi_nvidia_mcp_faster/mcp6x_spi.c =================================================================== --- flashrom-bitbang_spi_nvidia_mcp_faster/mcp6x_spi.c (Revision 1130) +++ flashrom-bitbang_spi_nvidia_mcp_faster/mcp6x_spi.c (Arbeitskopie) @@ -42,41 +42,39 @@ void *mcp6x_spibar = NULL; +/* Cached value of last GPIO state. */ +static uint8_t mcp_gpiostate; + static void mcp6x_request_spibus(void) { - uint8_t tmp; + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + mcp_gpiostate |= 1 << MCP6X_SPI_REQUEST; + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp |= 1 << MCP6X_SPI_REQUEST; - mmio_writeb(tmp, mcp6x_spibar + 0x530); - /* Wait until we are allowed to use the SPI bus. */ while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) ; + + /* Update the cache. */ + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); } static void mcp6x_release_spibus(void) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_REQUEST); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_REQUEST); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } static void mcp6x_bitbang_set_cs(int val) { - uint8_t tmp; - /* Requesting and releasing the SPI bus is handled in here to allow the * chipset to use its own SPI engine for native reads. */ if (val == 0) mcp6x_request_spibus(); - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_CS); - tmp |= (val << MCP6X_SPI_CS); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_CS); + mcp_gpiostate |= (val << MCP6X_SPI_CS); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); if (val == 1) mcp6x_release_spibus(); @@ -84,31 +82,22 @@ static void mcp6x_bitbang_set_sck(int val) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_SCK); - tmp |= (val << MCP6X_SPI_SCK); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_SCK); + mcp_gpiostate |= (val << MCP6X_SPI_SCK); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } static void mcp6x_bitbang_set_mosi(int val) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_MOSI); - tmp |= (val << MCP6X_SPI_MOSI); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_MOSI); + mcp_gpiostate |= (val << MCP6X_SPI_MOSI); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } static int mcp6x_bitbang_get_miso(void) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp = (tmp >> MCP6X_SPI_MISO) & 0x1; - return tmp; + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + return (mcp_gpiostate >> MCP6X_SPI_MISO) & 0x1; } static const struct bitbang_spi_master bitbang_spi_master_mcp6x = { @@ -176,9 +165,10 @@ msg_pdbg("SPI control is 0x%04x, req=%i, gnt=%i\n", status, (status >> MCP6X_SPI_REQUEST) & 0x1, (status >> MCP6X_SPI_GRANT) & 0x1); + mcp_gpiostate = status & 0xff; - /* 1 usec halfperiod delay for now. */ - if (bitbang_spi_init(&bitbang_spi_master_mcp6x, 1)) { + /* Zero halfperiod delay. */ + if (bitbang_spi_init(&bitbang_spi_master_mcp6x, 0)) { /* This should never happen. */ msg_perr("MCP6X bitbang SPI master init failed!\n"); return 1; -- http://www.hailfinger.org/

3 3

[commit] r1164 - trunk
by repository service 14 Sep '10

14 Sep '10

Author: hailfinger Date: Tue Sep 14 03:29:49 2010 New Revision: 1164 URL: http://flashrom.org/trac/flashrom/changeset/1164 Log: Use caching for Nvidia MCP SPI GPIO accesses. Reduce clock delay to zero. Tests show more than 2x speedup. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested-by: Andrew Morgan <ziltro(a)ziltro.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/mcp6x_spi.c Modified: trunk/mcp6x_spi.c ============================================================================== --- trunk/mcp6x_spi.c Tue Sep 14 01:00:57 2010 (r1163) +++ trunk/mcp6x_spi.c Tue Sep 14 03:29:49 2010 (r1164) @@ -42,41 +42,39 @@ void *mcp6x_spibar = NULL; +/* Cached value of last GPIO state. */ +static uint8_t mcp_gpiostate; + static void mcp6x_request_spibus(void) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp |= 1 << MCP6X_SPI_REQUEST; - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + mcp_gpiostate |= 1 << MCP6X_SPI_REQUEST; + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); /* Wait until we are allowed to use the SPI bus. */ while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) ; + + /* Update the cache. */ + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); } static void mcp6x_release_spibus(void) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_REQUEST); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_REQUEST); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } static void mcp6x_bitbang_set_cs(int val) { - uint8_t tmp; - /* Requesting and releasing the SPI bus is handled in here to allow the * chipset to use its own SPI engine for native reads. */ if (val == 0) mcp6x_request_spibus(); - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_CS); - tmp |= (val << MCP6X_SPI_CS); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_CS); + mcp_gpiostate |= (val << MCP6X_SPI_CS); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); if (val == 1) mcp6x_release_spibus(); @@ -84,31 +82,22 @@ static void mcp6x_bitbang_set_sck(int val) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_SCK); - tmp |= (val << MCP6X_SPI_SCK); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_SCK); + mcp_gpiostate |= (val << MCP6X_SPI_SCK); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } static void mcp6x_bitbang_set_mosi(int val) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_MOSI); - tmp |= (val << MCP6X_SPI_MOSI); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_MOSI); + mcp_gpiostate |= (val << MCP6X_SPI_MOSI); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } static int mcp6x_bitbang_get_miso(void) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp = (tmp >> MCP6X_SPI_MISO) & 0x1; - return tmp; + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + return (mcp_gpiostate >> MCP6X_SPI_MISO) & 0x1; } static const struct bitbang_spi_master bitbang_spi_master_mcp6x = { @@ -176,9 +165,10 @@ msg_pdbg("SPI control is 0x%04x, req=%i, gnt=%i\n", status, (status >> MCP6X_SPI_REQUEST) & 0x1, (status >> MCP6X_SPI_GRANT) & 0x1); + mcp_gpiostate = status & 0xff; - /* 1 usec halfperiod delay for now. */ - if (bitbang_spi_init(&bitbang_spi_master_mcp6x, 1)) { + /* Zero halfperiod delay. */ + if (bitbang_spi_init(&bitbang_spi_master_mcp6x, 0)) { /* This should never happen. */ msg_perr("MCP6X bitbang SPI master init failed!\n"); return 1;

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ASUS P5GD2 Premium
by Roberto Malinverni 14 Sep '10

14 Sep '10

Base Board Information from DMIDECODE: Manufacturer: ASUSTeK Computer INC. Product Name: P5GD2-Premium Version: Rev 1.xx Link to official firmware: I can't provide it due to the way Asus's site works... (I can upload my copy somewhere if you want) You have to search here http://support.asus.com/download/download.aspx?SLanguage=en-us filling the 3 search fields with: "motherboard" "socket 775" "p5gd2 premium" Attached are the requested logs.

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Re: [flashrom] ST M25PX32 and M25PX64 flash chip support
by Jason Shriver 14 Sep '10

14 Sep '10

Attached are the test results for the M25PX32 and M25PX64 flash chips. -----Original Message----- From: Jason Shriver [mailto:J.Shriver@F5.com] Sent: Monday, September 13, 2010 11:51 AM To: 'flashrom(a)flashrom.org' Subject: [flashrom] ST M25PX32 and M25PX64 flash chip support Add support for ST M25PX32 and M25PX64 flash chips. Probe, read, erase and write have been tested and all are functional. Signed-off-by: Jason Shriver <j.shriver(a)f5.com>

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flashrom September 2010