May 2010 - flashrom - mail.coreboot.org

Re: [flashrom] External programmers
by Mark Morschhäuser May 28, 2010

May 28, 2010

> 2. All those Willem/Sivava variants. People regularly request those, but > I don't think anyone in here owns the hardware. I bought the "Willem True USB Universal Programmer V2" with LPC/FWH adapter and would try to help out. I installed the software in virtualbox and e.g. could monitor the USB port when I am using the programmer. btw, everyone in the net seems to ask for the latest software... it can be downloaded from http://www.mcumall.com/comersus/store/mcumall_download.asp Greetings, Mark

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Part ASD 29F2008
by Néstor a.k.a. DarkMan May 28, 2010

May 28, 2010

Hi, I tried an ASD 29F2008 part and is recognized as a Winbond W29C020C. It fails at erase operation. How can I help to support the device? Motherboard: Shuttle AV11V30 Processor: Pentium III Chipset: Via Apollo Pro 133 Software version: flashrom v0.9.2-r1017 on Linux 2.6.24-27-generic (i686), built with libpci 2.2.4, GCC 4.2.4 (Ubuntu 4.2.4-1ubuntu4), little endian Greetings. _________________________________________________________________ Consejos para seducir ¿Puedes conocer gente nueva a través de Internet? ¡Regístrate ya! http://contactos.es.msn.com/?mtcmk=015352

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curious about nicrealtek
by Kyle Kienapfel May 28, 2010

May 28, 2010

Is probing the flash/eeprom something thats not done yet for rtl8139's? root@grayskull:~# flashrom -p nicrealtek flashrom v0.9.2-r1015 on Linux 2.6.17 (i686), built with libpci 3.0.0, GCC 4.4.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found "Realtek RTL8139/8139C/8139C+" (10ec:8139, BDF 02:0a.0). No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. I ran an strace on flashrom and just before it says theres no flash device it reads /sys/bus/pci/devices/0000\:02\:0a.0/config is this the contents of the eeprom where the bootrom size is configured? forcing a read works flashrom -p nicrealtek -f -r file -c SST29EE010

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[PATCH] Support 2-byte SPI RES command
by Carl-Daniel Hailfinger May 28, 2010

May 28, 2010

Some chips implement the RES (0xab) opcode, but they use a non-standard two byte response instead of the usual one byte response. A two-byte response has the accuracy of REMS and RDID, so don't check for REMS/RDID availability before running a two-byte RES. Side note: The one-byte RES will fail on wbsio, but it did that in old versions as well. This needs to be fixed in wbsio. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_2byte_res/spi25.c =================================================================== --- flashrom-spi_2byte_res/spi25.c (Revision 1016) +++ flashrom-spi_2byte_res/spi25.c (Arbeitskopie) @@ -67,20 +67,20 @@ return 0; } -static int spi_res(unsigned char *readarr) +static int spi_res(unsigned char *readarr, int bytes) { unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; uint32_t readaddr; int ret; - ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { /* Find the lowest even address allowed for reads. */ readaddr = (spi_get_valid_read_addr() + 1) & ~1; cmd[1] = (readaddr >> 16) & 0xff, cmd[2] = (readaddr >> 8) & 0xff, cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); } if (ret) return ret; @@ -235,13 +235,15 @@ return 0; } -int probe_spi_res(struct flashchip *flash) +int probe_spi_res1(struct flashchip *flash) { unsigned char readarr[3]; uint32_t id2; const unsigned char allff[] = {0xff, 0xff, 0xff}; const unsigned char all00[] = {0x00, 0x00, 0x00}; + /* We only want one-byte RES if RDID and REMS are unusable. */ + /* Check if RDID is usable and does not return 0xff 0xff 0xff or * 0x00 0x00 0x00. In that case, RES is pointless. */ @@ -259,12 +261,13 @@ return 0; } - if (spi_res(readarr)) + if (spi_res(readarr, 1)) return 0; - /* FIXME: Handle the case where RES gives a 2-byte response. */ id2 = readarr[0]; + msg_cdbg("%s: id 0x%x\n", __func__, id2); + if (id2 != flash->model_id) return 0; @@ -275,6 +278,29 @@ return 1; } +int probe_spi_res2(struct flashchip *flash) +{ + unsigned char readarr[2]; + uint32_t id1, id2; + + if (spi_res(readarr, 2)) + return 0; + + id1 = readarr[0]; + id2 = readarr[1]; + + msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2); + + if (id1 != flash->manufacture_id || id2 != flash->model_id) + return 0; + + /* Print the status register to tell the + * user about possible write protection. + */ + spi_prettyprint_status_register(flash); + return 1; +} + uint8_t spi_read_status_register(void) { const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; Index: flashrom-spi_2byte_res/flashchips.c =================================================================== --- flashrom-spi_2byte_res/flashchips.c (Revision 1016) +++ flashrom-spi_2byte_res/flashchips.c (Arbeitskopie) @@ -4665,19 +4665,19 @@ /* The ST M25P05 is a bit of a problem. It has the same ID as the * ST M25P05-A in RES mode, but supports only 128 byte writes instead - * of 256 byte writes. We rely heavily on the fact that probe_spi_res + * of 256 byte writes. We rely heavily on the fact that probe_spi_res1 * only is successful if RDID does not work. */ { .vendor = "ST", .name = "M25P05.RES", .bustype = CHIP_BUSTYPE_SPI, - .manufacture_id = ST_ID, + .manufacture_id = 0, /* Not used. */ .model_id = ST_M25P05_RES, .total_size = 64, .page_size = 256, .tested = TEST_UNTESTED, - .probe = probe_spi_res, + .probe = probe_spi_res1, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -4723,12 +4723,12 @@ .vendor = "ST", .name = "M25P10.RES", .bustype = CHIP_BUSTYPE_SPI, - .manufacture_id = ST_ID, + .manufacture_id = 0, /* Not used. */ .model_id = ST_M25P10_RES, .total_size = 128, .page_size = 256, .tested = TEST_UNTESTED, - .probe = probe_spi_res, + .probe = probe_spi_res1, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -4798,12 +4798,12 @@ .vendor = "ST", .name = "M25P40-old", .bustype = CHIP_BUSTYPE_SPI, - .manufacture_id = ST_ID, + .manufacture_id = 0, /* Not used. */ .model_id = ST_M25P40_RES, .total_size = 512, .page_size = 256, .tested = TEST_UNTESTED, - .probe = probe_spi_res, + .probe = probe_spi_res1, .probe_timing = TIMING_ZERO, .block_erasers = { Index: flashrom-spi_2byte_res/spi.h =================================================================== --- flashrom-spi_2byte_res/spi.h (Revision 1016) +++ flashrom-spi_2byte_res/spi.h (Arbeitskopie) @@ -27,6 +27,7 @@ /* Read Electronic ID */ #define JEDEC_RDID 0x9f #define JEDEC_RDID_OUTSIZE 0x01 +/* INSIZE may be 0x04 for some chips*/ #define JEDEC_RDID_INSIZE 0x03 /* AT25F512A has bit 3 as don't care bit in commands */ @@ -42,6 +43,7 @@ /* Read Electronic Signature */ #define JEDEC_RES 0xab #define JEDEC_RES_OUTSIZE 0x04 +/* INSIZE may be 0x02 for some chips*/ #define JEDEC_RES_INSIZE 0x01 /* Write Enable */ Index: flashrom-spi_2byte_res/chipdrivers.h =================================================================== --- flashrom-spi_2byte_res/chipdrivers.h (Revision 1016) +++ flashrom-spi_2byte_res/chipdrivers.h (Arbeitskopie) @@ -29,7 +29,8 @@ int probe_spi_rdid(struct flashchip *flash); int probe_spi_rdid4(struct flashchip *flash); int probe_spi_rems(struct flashchip *flash); -int probe_spi_res(struct flashchip *flash); +int probe_spi_res1(struct flashchip *flash); +int probe_spi_res2(struct flashchip *flash); int spi_write_enable(void); int spi_write_disable(void); int spi_chip_erase_60(struct flashchip *flash); -- http://www.hailfinger.org/

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[commit] r1017 - trunk
by repository service May 28, 2010

May 28, 2010

Author: hailfinger Date: Fri May 28 19:07:57 2010 New Revision: 1017 URL: http://flashrom.org/trac/coreboot/changeset/1017 Log: Some chips implement the RES (0xab) opcode, but they use a non-standard two byte response instead of the usual one byte response. A two-byte response has the accuracy of REMS and RDID, so don't check for REMS/RDID availability before running a two-byte RES. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/chipdrivers.h trunk/flashchips.c trunk/spi.h trunk/spi25.c Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Fri May 28 17:53:08 2010 (r1016) +++ trunk/chipdrivers.h Fri May 28 19:07:57 2010 (r1017) @@ -29,7 +29,8 @@ int probe_spi_rdid(struct flashchip *flash); int probe_spi_rdid4(struct flashchip *flash); int probe_spi_rems(struct flashchip *flash); -int probe_spi_res(struct flashchip *flash); +int probe_spi_res1(struct flashchip *flash); +int probe_spi_res2(struct flashchip *flash); int spi_write_enable(void); int spi_write_disable(void); int spi_chip_erase_60(struct flashchip *flash); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Fri May 28 17:53:08 2010 (r1016) +++ trunk/flashchips.c Fri May 28 19:07:57 2010 (r1017) @@ -4665,19 +4665,19 @@ /* The ST M25P05 is a bit of a problem. It has the same ID as the * ST M25P05-A in RES mode, but supports only 128 byte writes instead - * of 256 byte writes. We rely heavily on the fact that probe_spi_res + * of 256 byte writes. We rely heavily on the fact that probe_spi_res1 * only is successful if RDID does not work. */ { .vendor = "ST", .name = "M25P05.RES", .bustype = CHIP_BUSTYPE_SPI, - .manufacture_id = ST_ID, + .manufacture_id = 0, /* Not used. */ .model_id = ST_M25P05_RES, .total_size = 64, .page_size = 256, .tested = TEST_UNTESTED, - .probe = probe_spi_res, + .probe = probe_spi_res1, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -4723,12 +4723,12 @@ .vendor = "ST", .name = "M25P10.RES", .bustype = CHIP_BUSTYPE_SPI, - .manufacture_id = ST_ID, + .manufacture_id = 0, /* Not used. */ .model_id = ST_M25P10_RES, .total_size = 128, .page_size = 256, .tested = TEST_UNTESTED, - .probe = probe_spi_res, + .probe = probe_spi_res1, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -4798,12 +4798,12 @@ .vendor = "ST", .name = "M25P40-old", .bustype = CHIP_BUSTYPE_SPI, - .manufacture_id = ST_ID, + .manufacture_id = 0, /* Not used. */ .model_id = ST_M25P40_RES, .total_size = 512, .page_size = 256, .tested = TEST_UNTESTED, - .probe = probe_spi_res, + .probe = probe_spi_res1, .probe_timing = TIMING_ZERO, .block_erasers = { Modified: trunk/spi.h ============================================================================== --- trunk/spi.h Fri May 28 17:53:08 2010 (r1016) +++ trunk/spi.h Fri May 28 19:07:57 2010 (r1017) @@ -27,6 +27,7 @@ /* Read Electronic ID */ #define JEDEC_RDID 0x9f #define JEDEC_RDID_OUTSIZE 0x01 +/* INSIZE may be 0x04 for some chips*/ #define JEDEC_RDID_INSIZE 0x03 /* AT25F512A has bit 3 as don't care bit in commands */ @@ -42,6 +43,7 @@ /* Read Electronic Signature */ #define JEDEC_RES 0xab #define JEDEC_RES_OUTSIZE 0x04 +/* INSIZE may be 0x02 for some chips*/ #define JEDEC_RES_INSIZE 0x01 /* Write Enable */ Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Fri May 28 17:53:08 2010 (r1016) +++ trunk/spi25.c Fri May 28 19:07:57 2010 (r1017) @@ -67,20 +67,20 @@ return 0; } -static int spi_res(unsigned char *readarr) +static int spi_res(unsigned char *readarr, int bytes) { unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; uint32_t readaddr; int ret; - ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { /* Find the lowest even address allowed for reads. */ readaddr = (spi_get_valid_read_addr() + 1) & ~1; cmd[1] = (readaddr >> 16) & 0xff, cmd[2] = (readaddr >> 8) & 0xff, cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); } if (ret) return ret; @@ -235,13 +235,15 @@ return 0; } -int probe_spi_res(struct flashchip *flash) +int probe_spi_res1(struct flashchip *flash) { unsigned char readarr[3]; uint32_t id2; const unsigned char allff[] = {0xff, 0xff, 0xff}; const unsigned char all00[] = {0x00, 0x00, 0x00}; + /* We only want one-byte RES if RDID and REMS are unusable. */ + /* Check if RDID is usable and does not return 0xff 0xff 0xff or * 0x00 0x00 0x00. In that case, RES is pointless. */ @@ -259,16 +261,40 @@ return 0; } - if (spi_res(readarr)) + if (spi_res(readarr, 1)) return 0; - /* FIXME: Handle the case where RES gives a 2-byte response. */ id2 = readarr[0]; + msg_cdbg("%s: id 0x%x\n", __func__, id2); + if (id2 != flash->model_id) return 0; /* Print the status register to tell the + * user about possible write protection. + */ + spi_prettyprint_status_register(flash); + return 1; +} + +int probe_spi_res2(struct flashchip *flash) +{ + unsigned char readarr[2]; + uint32_t id1, id2; + + if (spi_res(readarr, 2)) + return 0; + + id1 = readarr[0]; + id2 = readarr[1]; + + msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2); + + if (id1 != flash->manufacture_id || id2 != flash->model_id) + return 0; + + /* Print the status register to tell the * user about possible write protection. */ spi_prettyprint_status_register(flash);

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[PATCH] Avoid transaction errors on ICH SPI
by Carl-Daniel Hailfinger May 28, 2010

May 28, 2010

ICH SPI can enforces address restrictions for all accesses which take an address (well, it could if the chipset implementation was not broken). Since exploiting the broken implementation is harder than conforming to the address restrictions wherever possible, conform to the address restrictions instead. This patch will eliminate a lot of transaction errors people were seeing (for probe, anyway). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ichspi_avoid_transaction_error_use_bbar/flash.h =================================================================== --- flashrom-ichspi_avoid_transaction_error_use_bbar/flash.h (Revision 1015) +++ flashrom-ichspi_avoid_transaction_error_use_bbar/flash.h (Arbeitskopie) @@ -663,6 +663,8 @@ uint32_t spi_get_valid_read_addr(void); /* ichspi.c */ +extern int ichspi_lock; +extern uint32_t ichspi_bbar; int ich_init_opcodes(void); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); Index: flashrom-ichspi_avoid_transaction_error_use_bbar/spi.c =================================================================== --- flashrom-ichspi_avoid_transaction_error_use_bbar/spi.c (Revision 1015) +++ flashrom-ichspi_avoid_transaction_error_use_bbar/spi.c (Arbeitskopie) @@ -207,8 +207,22 @@ return spi_programmer[spi_controller].write_256(flash, buf); } +/* + * Get the lowest allowed address for read accesses. This often happens to + * be the lowest allowed address for all commands which take an address. + * This is a programmer limitation. + */ uint32_t spi_get_valid_read_addr(void) { - /* Need to return BBAR for ICH chipsets. */ - return 0; + switch (spi_controller) { +#if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) + case SPI_CONTROLLER_ICH7: + /* Return BBAR for ICH chipsets. */ + return ichspi_bbar; +#endif +#endif + default: + return 0; + } } Index: flashrom-ichspi_avoid_transaction_error_use_bbar/chipset_enable.c =================================================================== --- flashrom-ichspi_avoid_transaction_error_use_bbar/chipset_enable.c (Revision 1015) +++ flashrom-ichspi_avoid_transaction_error_use_bbar/chipset_enable.c (Arbeitskopie) @@ -36,8 +36,6 @@ #if defined(__i386__) || defined(__x86_64__) -extern int ichspi_lock; - static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) { uint8_t tmp; @@ -515,8 +513,9 @@ msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, mmio_readl(spibar + offs + 4), i); } + ichspi_bbar = mmio_readl(spibar + 0x50); msg_pdbg("0x50: 0x%08x (BBAR)\n", - mmio_readl(spibar + 0x50)); + ichspi_bbar); msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(spibar + 0x54)); msg_pdbg("0x56: 0x%04x (OPTYPE)\n", @@ -587,8 +586,9 @@ mmio_readl(spibar + 0x98)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(spibar + 0x9C)); + ichspi_bbar = mmio_readl(spibar + 0xA0); msg_pdbg("0xA0: 0x%08x (BBAR)\n", - mmio_readl(spibar + 0xA0)); + ichspi_bbar); msg_pdbg("0xB0: 0x%08x (FDOC)\n", mmio_readl(spibar + 0xB0)); if (tmp2 & (1 << 15)) { Index: flashrom-ichspi_avoid_transaction_error_use_bbar/ichspi.c =================================================================== --- flashrom-ichspi_avoid_transaction_error_use_bbar/ichspi.c (Revision 1015) +++ flashrom-ichspi_avoid_transaction_error_use_bbar/ichspi.c (Arbeitskopie) @@ -103,6 +103,8 @@ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ int ichspi_lock = 0; +uint32_t ichspi_bbar = 0; + typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode uint8_t spi_type; //This commands spi type @@ -327,6 +329,35 @@ return 0; } +/* + * Try to set BBAR (BIOS Base Address Register), but read back the value in case + * it didn't stick. + */ +void ich_set_bbar(uint32_t minaddr) +{ + switch (spi_controller) { + case SPI_CONTROLLER_ICH7: + mmio_writel(minaddr, spibar + 0x50); + ichspi_bbar = mmio_readl(spibar + 0x50); + /* We don't have any option except complaining. */ + if (ichspi_bbar != minaddr) + msg_perr("Setting BBAR failed!\n"); + break; + case SPI_CONTROLLER_ICH9: + mmio_writel(minaddr, spibar + 0xA0); + ichspi_bbar = mmio_readl(spibar + 0xA0); + /* We don't have any option except complaining. */ + if (ichspi_bbar != minaddr) + msg_perr("Setting BBAR failed!\n"); + break; + default: + /* Not sure if BBAR actually exists on VIA. */ + msg_pdbg("Setting BBAR is not implemented for VIA yet.\n"); + break; + } + +} + /* This function generates OPCODES from or programs OPCODES to ICH according to * the chipset's SPI configuration lock. * @@ -341,13 +372,18 @@ return 0; if (ichspi_lock) { - msg_pdbg("Generating OPCODES... "); + msg_pdbg("Reading OPCODES... "); curopcodes_done = &O_EXISTING; rc = generate_opcodes(curopcodes_done); } else { msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; rc = program_opcodes(curopcodes_done); + /* Technically not part of opcode init, but it allows opcodes + * to run without transaction errors by setting the lowest + * allowed address to zero. + */ + ich_set_bbar(0); } if (rc) { -- http://www.hailfinger.org/

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[commit] r1016 - trunk
by repository service May 28, 2010

May 28, 2010

Author: hailfinger Date: Fri May 28 17:53:08 2010 New Revision: 1016 URL: http://flashrom.org/trac/coreboot/changeset/1016 Log: ICH SPI can enforce address restrictions for all accesses which take an address (well, it could if the chipset implementation was not broken). Since exploiting the broken implementation is harder than conforming to the address restrictions wherever possible, conform to the address restrictions instead. This patch eliminates a lot of transaction errors people were seeing on chip probe. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/chipset_enable.c trunk/flash.h trunk/ichspi.c trunk/spi.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Thu May 27 00:29:51 2010 (r1015) +++ trunk/chipset_enable.c Fri May 28 17:53:08 2010 (r1016) @@ -36,8 +36,6 @@ #if defined(__i386__) || defined(__x86_64__) -extern int ichspi_lock; - static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) { uint8_t tmp; @@ -515,8 +513,9 @@ msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, mmio_readl(spibar + offs + 4), i); } + ichspi_bbar = mmio_readl(spibar + 0x50); msg_pdbg("0x50: 0x%08x (BBAR)\n", - mmio_readl(spibar + 0x50)); + ichspi_bbar); msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(spibar + 0x54)); msg_pdbg("0x56: 0x%04x (OPTYPE)\n", @@ -587,8 +586,9 @@ mmio_readl(spibar + 0x98)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(spibar + 0x9C)); + ichspi_bbar = mmio_readl(spibar + 0xA0); msg_pdbg("0xA0: 0x%08x (BBAR)\n", - mmio_readl(spibar + 0xA0)); + ichspi_bbar); msg_pdbg("0xB0: 0x%08x (FDOC)\n", mmio_readl(spibar + 0xB0)); if (tmp2 & (1 << 15)) { Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Thu May 27 00:29:51 2010 (r1015) +++ trunk/flash.h Fri May 28 17:53:08 2010 (r1016) @@ -663,6 +663,8 @@ uint32_t spi_get_valid_read_addr(void); /* ichspi.c */ +extern int ichspi_lock; +extern uint32_t ichspi_bbar; int ich_init_opcodes(void); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Thu May 27 00:29:51 2010 (r1015) +++ trunk/ichspi.c Fri May 28 17:53:08 2010 (r1016) @@ -103,6 +103,8 @@ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ int ichspi_lock = 0; +uint32_t ichspi_bbar = 0; + typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode uint8_t spi_type; //This commands spi type @@ -327,6 +329,34 @@ return 0; } +/* + * Try to set BBAR (BIOS Base Address Register), but read back the value in case + * it didn't stick. + */ +void ich_set_bbar(uint32_t minaddr) +{ + switch (spi_controller) { + case SPI_CONTROLLER_ICH7: + mmio_writel(minaddr, spibar + 0x50); + ichspi_bbar = mmio_readl(spibar + 0x50); + /* We don't have any option except complaining. */ + if (ichspi_bbar != minaddr) + msg_perr("Setting BBAR failed!\n"); + break; + case SPI_CONTROLLER_ICH9: + mmio_writel(minaddr, spibar + 0xA0); + ichspi_bbar = mmio_readl(spibar + 0xA0); + /* We don't have any option except complaining. */ + if (ichspi_bbar != minaddr) + msg_perr("Setting BBAR failed!\n"); + break; + default: + /* Not sure if BBAR actually exists on VIA. */ + msg_pdbg("Setting BBAR is not implemented for VIA yet.\n"); + break; + } +} + /* This function generates OPCODES from or programs OPCODES to ICH according to * the chipset's SPI configuration lock. * @@ -341,13 +371,18 @@ return 0; if (ichspi_lock) { - msg_pdbg("Generating OPCODES... "); + msg_pdbg("Reading OPCODES... "); curopcodes_done = &O_EXISTING; rc = generate_opcodes(curopcodes_done); } else { msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; rc = program_opcodes(curopcodes_done); + /* Technically not part of opcode init, but it allows opcodes + * to run without transaction errors by setting the lowest + * allowed address to zero. + */ + ich_set_bbar(0); } if (rc) { @@ -743,6 +778,19 @@ opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); + switch (spi_controller) { + case SPI_CONTROLLER_ICH7: + case SPI_CONTROLLER_ICH9: + if (addr < ichspi_bbar) { + msg_perr("%s: Address 0x%06x below allowed " + "range 0x%06x-0xffffff\n", __func__, + addr, ichspi_bbar); + return SPI_INVALID_ADDRESS; + } + break; + default: + break; + } } /* translate read/write array/count */ Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Thu May 27 00:29:51 2010 (r1015) +++ trunk/spi.c Fri May 28 17:53:08 2010 (r1016) @@ -207,8 +207,22 @@ return spi_programmer[spi_controller].write_256(flash, buf); } +/* + * Get the lowest allowed address for read accesses. This often happens to + * be the lowest allowed address for all commands which take an address. + * This is a programmer limitation. + */ uint32_t spi_get_valid_read_addr(void) { - /* Need to return BBAR for ICH chipsets. */ - return 0; + switch (spi_controller) { +#if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) + case SPI_CONTROLLER_ICH7: + /* Return BBAR for ICH chipsets. */ + return ichspi_bbar; +#endif +#endif + default: + return 0; + } }

1 0

[PATCH 1/3] Sort boards alphabetically.
by Peter Lemenkov May 26, 2010

May 26, 2010

Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- board_enable.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board_enable.c b/board_enable.c index 4251601..963bf58 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1402,12 +1402,12 @@ struct board_pciid_enable board_pciid_enables[] = { {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "Abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, - {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, + {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, @@ -1457,9 +1457,9 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, - {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL}, {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, + {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, #endif -- 1.6.6.1

2 2

[PATCH 2/3] This board is not an 'Albatron PM266A' but a 'Albatron PM266A Pro'.
by Peter Lemenkov May 26, 2010

May 26, 2010

It seems that this board is actually a 'Pro' version. At least it's addressed as 'Pro' in the list of boards, which requires board_enable. Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- board_enable.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board_enable.c b/board_enable.c index 963bf58..f6462d9 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1403,7 +1403,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, - {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, + {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, -- 1.6.6.1

2 1

[commit] r1015 - trunk
by repository service May 26, 2010

May 26, 2010

Author: uwe Date: Thu May 27 00:29:51 2010 New Revision: 1015 URL: http://flashrom.org/trac/coreboot/changeset/1015 Log: It seems that this board is actually a 'Pro' version. At least it's addressed as 'Pro' in the list of boards, which requires board_enable. See also: http://www.flashrom.org/pipermail/flashrom/2009-July/000003.html Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu May 27 00:26:44 2010 (r1014) +++ trunk/board_enable.c Thu May 27 00:29:51 2010 (r1015) @@ -1403,7 +1403,7 @@ {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, - {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, + {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},

1 0