flashrom May 2010

flashrom@flashrom.org

64 participants
169 discussions

Re: [flashrom] [PATCH] Unlocking for W39V040FA
by Uwe Hermann 30 May '10

30 May '10

On Sat, May 15, 2010 at 09:19:23PM +0200, Michael Karcher wrote: > Now added the missing "REGISTERMAP" feature. Tested on hardware according to http://www.flashrom.org/pipermail/flashrom/2010-May/003078.html So: Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[PATCH] Add hp xw9400 board enable.
by Michael Karcher 30 May '10

30 May '10

Reduced version - please check whether it works, too. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 42 ++++++++++++++++++++++++++++++++++-------- 1 files changed, 34 insertions(+), 8 deletions(-) diff --git a/board_enable.c b/board_enable.c index b5eb63f..cd15a0f 100644 --- a/board_enable.c +++ b/board_enable.c @@ -552,6 +552,7 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) { struct pci_dev *dev; uint16_t base; + uint16_t devclass; uint8_t tmp; if ((gpio < 0) || (gpio >= 0x40)) { @@ -566,17 +567,33 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) case 0x0050: /* MCP04 */ case 0x0060: /* MCP2 */ break; - default: - /* Newer MCPs use the SMBus Controller */ - dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); - switch (dev->device_id) { - case 0x0264: /* MCP51 */ + case 0x0260: /* MCP51 */ + case 0x0364: /* MCP55 */ + /* find SMBus controller on *this* southbridge */ + /* The infamous Tyan S2915-E has two south bridges; they are + easily told apart from each other by the class of the + LPC bridge, but have the same SMBus bridge IDs */ + if (dev->func != 0) { + msg_perr("MCP LCP bridge at unexpected function" + " number %d\n", dev->func); + return -1; + } + + dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1); + if (!dev) { + msg_perr("MCP SMBus controller could not be found\n"); + return -1; + } + devclass = pci_read_word(dev, 0x0a); + if (devclass != 0x0C05) { + msg_perr("Unexpected device class %04x for SMBus" + " controller\n", devclass); + return -1; + } break; - default: + default: msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n"); return -1; - } - break; } base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ @@ -651,6 +668,14 @@ static int nvidia_mcp_gpio31_raise(const char *name) } /** + * Suited for HP xw9400 (Tyan S2915-E OEM): nVidia MCP55. + */ +static int board_hp_xw9400(const char *name) +{ + return nvidia_mcp_gpio_set(0x05, 1); +} + +/** * Suited for Artec Group DBE61 and DBE62. */ static int board_artecgroup_dbe6x(const char *name) @@ -1437,6 +1462,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, + {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, board_hp_xw9400}, {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "iBASE", "MB899", 0, NT, intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, -- 1.7.1

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Re: [flashrom] [PATCH] Fix handling of empty dmidecode output
by Carl-Daniel Hailfinger 30 May '10

30 May '10

On 24.03.2010 17:58, Michael Karcher wrote: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

Working board
by Bas Heijermans 30 May '10

30 May '10

Hi, I tested the MSI DKA790GX Platinum (MS-7550) and it flashed fine, no problems at all. Bas.

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[PATCH] Add hp xw9400 board enable.
by Michael Karcher 30 May '10

30 May '10

Now checks for the right SMBus device and is compilable. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++------- 1 files changed, 51 insertions(+), 8 deletions(-) diff --git a/board_enable.c b/board_enable.c index b5eb63f..2f3a6f4 100644 --- a/board_enable.c +++ b/board_enable.c @@ -552,6 +552,7 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) { struct pci_dev *dev; uint16_t base; + uint16_t devclass; uint8_t tmp; if ((gpio < 0) || (gpio >= 0x40)) { @@ -566,17 +567,33 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) case 0x0050: /* MCP04 */ case 0x0060: /* MCP2 */ break; - default: - /* Newer MCPs use the SMBus Controller */ - dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); - switch (dev->device_id) { - case 0x0264: /* MCP51 */ + case 0x0260: /* MCP51 */ + case 0x0364: /* MCP55 */ + /* find SMBus controller on *this* southbridge */ + /* The infamous Tyan S2915-E has two south bridges; they are + easily told apart from each other by the class of the + LPC bridge, but have the same SMBus bridge IDs */ + if (dev->func != 0) { + msg_perr("MCP LCP bridge at unexpected function" + " number %d\n", dev->func); + return -1; + } + + dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1); + if (!dev) { + msg_perr("MCP SMBus controller could not be found\n"); + return -1; + } + devclass = pci_read_word(dev, 0x0a); + if (devclass != 0x0C05) { + msg_perr("Unexpected device class %04x for SMBus" + " controller\n", devclass); + return -1; + } break; - default: + default: msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n"); return -1; - } - break; } base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ @@ -651,6 +668,31 @@ static int nvidia_mcp_gpio31_raise(const char *name) } /** + * Suited for HP xw9400 (Tyan S2915-E OEM): nVidia MCP55. + */ +static int board_hp_xw9400(const char *name) +{ + struct pci_dev * dev; + uint16_t base; + uint16_t tmp; + dev = pci_get_dev(pacc, 0, 0, 1, 1); /* UGLY HACK! */ + if(!dev) { + fprintf(stderr, "SMBus bridge not found?!\n"); + return -1; + } + base = pci_read_long(dev,0x60) & 0xFF00; + if(base < 0x400) { + fprintf(stderr, "bogus I/O base %04x\n", base); + return -1; + } + tmp = INW(base+2); + tmp &= 0xFEFF; + OUTW(tmp, base+2); + + return nvidia_mcp_gpio_set(0x05, 1); +} + +/** * Suited for Artec Group DBE61 and DBE62. */ static int board_artecgroup_dbe6x(const char *name) @@ -1437,6 +1479,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, + {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, board_hp_xw9400}, {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "iBASE", "MB899", 0, NT, intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, -- 1.7.1

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[PATCH] Add hp xw9400 board enable.
by Michael Karcher 30 May '10

30 May '10

Now makes sure to pick the right SMBus bridge. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++------- 1 files changed, 51 insertions(+), 8 deletions(-) diff --git a/board_enable.c b/board_enable.c index b5eb63f..f77ab41 100644 --- a/board_enable.c +++ b/board_enable.c @@ -552,6 +552,7 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) { struct pci_dev *dev; uint16_t base; + uint16_t devclass; uint8_t tmp; if ((gpio < 0) || (gpio >= 0x40)) { @@ -566,17 +567,33 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) case 0x0050: /* MCP04 */ case 0x0060: /* MCP2 */ break; - default: - /* Newer MCPs use the SMBus Controller */ - dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); - switch (dev->device_id) { - case 0x0264: /* MCP51 */ + case 0x0260: /* MCP51 */ + case 0x0364: /* MCP55 */ + /* find SMBus controller on *this* southbridge */ + /* The infamous Tyan S2915-E has two south bridges; they are + easily told apart from each other by the class of the + LPC bridge, but have the same SMBus bridge IDs */ + if (dev->func != 0) { + msg_perr("MCP LCP bridge at unexpected function" + " number %d\n", dev->func); + return -1; + } + + dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1); + if (!dev) { + msg_perr("MCP SMBus controller could not be found\n"); + return -1; + } + devclass = pci_read_word(dev, 0x0a); + if (devclass != 0x0C05) { + msg_perr("Unexpected device class %04x for SMBus" + " controller\n", devclass); + return -1; + } break; - default: + default: msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n"); return -1; - } - break; } base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ @@ -651,6 +668,31 @@ static int nvidia_mcp_gpio31_raise(const char *name) } /** + * Suited for HP xw9400 (Tyan S2915-E OEM): nVidia MCP55. + */ +static int board_hp_xw9400(const char *name) +{ + struct pci_dev * dev; + uint16_t base; + uint16_t tmp; + dev = pci_dev_get(0, 0, 1, 1); /* UGLY HACK! */ + if(!dev) { + fprintf(stderr, "SMBus bridge not found?!\n"); + return -1; + } + base = pci_read_long(dev,0x60) & 0xFF00; + if(base < 0x400) { + fprintf(stderr, "bogus I/O base %04x\n", base); + return -1; + } + tmp = INW(base+2); + tmp &= 0xFEFF; + OUTW(tmp, base+2); + + return nvidia_mcp_gpio_set(0x05, 1); +} + +/** * Suited for Artec Group DBE61 and DBE62. */ static int board_artecgroup_dbe6x(const char *name) @@ -1437,6 +1479,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, + {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, board_hp_xw9400}, {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "iBASE", "MB899", 0, NT, intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, -- 1.7.1

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[PATCH] Add hp xw9400 board enable.
by Michael Karcher 30 May '10

30 May '10

Third try... Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index b5eb63f..270f713 100644 --- a/board_enable.c +++ b/board_enable.c @@ -571,6 +571,7 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); switch (dev->device_id) { case 0x0264: /* MCP51 */ + case 0x0364: /* MCP55 */ break; default: msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n"); @@ -651,6 +652,31 @@ static int nvidia_mcp_gpio31_raise(const char *name) } /** + * Suited for HP xw9400 (Tyan S2915-E OEM): nVidia MCP55. + */ +static int board_hp_xw9400(const char *name) +{ + struct pci_dev * dev; + uint16_t base; + uint16_t tmp; + dev = pci_dev_find(0x10de,0x0364); + if(!dev) { + fprintf(stderr, "SMBus bridge not found?!\n"); + return -1; + } + base = pci_read_long(dev,0x60) & 0xFF00; + if(base < 0x400) { + fprintf(stderr, "bogus I/O base %04x\n", base); + return -1; + } + tmp = INW(base+2); + tmp &= 0xFEFF; + OUTW(tmp, base+2); + + return nvidia_mcp_gpio_set(0x05, 1); +} + +/** * Suited for Artec Group DBE61 and DBE62. */ static int board_artecgroup_dbe6x(const char *name) @@ -1437,6 +1463,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, + {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, board_hp_xw9400}, {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "iBASE", "MB899", 0, NT, intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, -- 1.7.1

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[PATCH] Add hp xw9400 board enable.
by Michael Karcher 30 May '10

30 May '10

Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index b5eb63f..a67f0b9 100644 --- a/board_enable.c +++ b/board_enable.c @@ -571,6 +571,7 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); switch (dev->device_id) { case 0x0264: /* MCP51 */ + case 0x0364: /* MCP55 */ break; default: msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n"); @@ -619,6 +620,14 @@ static int nvidia_mcp_gpio2_raise(const char *name) } /** + * Suited for HP xw9400 (Tyan S2915-E OEM): nVidia MCP55. + */ +static int nvidia_mcp_gpio5_raise(const char *name) +{ + return nvidia_mcp_gpio_set(0x05, 1); +} + +/** * Suited for Abit NF7-S: NVIDIA CK804. */ static int nvidia_mcp_gpio8_raise(const char *name) @@ -1437,6 +1446,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, + {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise}, {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "iBASE", "MB899", 0, NT, intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, -- 1.7.1

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Re: [flashrom] [PATCH] experimental patch for HP branded Tyan S2915
by Carl-Daniel Hailfinger 30 May '10

30 May '10

Hi, On 28.01.2010 16:36, Michael Karcher wrote: > This patch may or may not help the HP xw9400 workstation [...] > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > Turns out that this patch was not needed for flash detection, but it may be needed as board enable for writing. Besides that, it allows MCP55 GPIO access which we need anyway. > diff --git a/board_enable.c b/board_enable.c > index 2c836a9..6970be2 100644 > --- a/board_enable.c > +++ b/board_enable.c > @@ -478,6 +478,7 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) > dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); > switch (dev->device_id) { > case 0x0264: /* MCP51 */ > + case 0x0364: /* MCP55 */ > break; > default: > fprintf(stderr, > @@ -513,6 +514,26 @@ static int nvidia_mcp_gpio2_raise(const char *name) > */ > static int nvidia_mcp_gpio5_raise(const char *name) > { > + /* experimental stuff - maybe it helps the hidden flash > + chip problem on Tyan S2915-E */ > + struct pci_dev * dev; > + uint16_t base; > + uint16_t tmp; > + dev = pci_dev_find(0x10de,0x0364); > + if(!dev) { > + fprintf(stderr, "SMBus bridge not found?!\n"); > + return -1; > + } > + base = pci_read_long(dev,0x60) & 0xFF00; > + if(base < 0x400) { > + fprintf(stderr, "bogus I/O base %04x\n", base); > + return -1; > + } > + tmp = INW(base+2); > + tmp &= 0xFEFF; > + OUTW(tmp, base+2); > + > + /* Obvious stuff for the HP variant */ > return nvidia_mcp_gpio_set(0x05, 1); > } > > Regards, Carl-Daniel -- http://www.hailfinger.org/

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[RFC] Making flashrom standalone on Yeeloong
by Vladimir 'φ-coder/phcoder' Serbinenko 29 May '10

29 May '10

Hello, all. As a side projetc I wanted to make flashrom loadable using multiboot2 protocol on yeeloong. In this case multiboot2-compliant loader will already put the necessary files in memory so no FS code is required. Major changes: Remove OS includes, disable few secondary files, write standalone analoga for standard functions, write initialisations, use passed buffers instead of files and the most intrusive change is switch to static allocation. The patch still doesn't compile, I posting it here only for idea gathering -- Regards Vladimir 'φ-coder/phcoder' Serbinenko

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flashrom May 2010