flashrom May 2010

flashrom@flashrom.org

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169 discussions

[PATCH 1/2] convert programmer print messages to msg_p*
by Sean Nelson 07 May '10

07 May '10

--- board_enable.c | 93 +++++++++++------------ cbtable.c | 26 +++--- chipset_enable.c | 216 +++++++++++++++++++++++++++--------------------------- dmi.c | 12 ++-- hwaccess.c | 2 +- ichspi.c | 77 ++++++++----------- internal.c | 4 +- pcidev.c | 12 ++-- physmap.c | 34 ++++---- spi.c | 8 +- 10 files changed, 235 insertions(+), 249 deletions(-) diff --git a/board_enable.c b/board_enable.c index 9b05f76..9112011 100644 --- a/board_enable.c +++ b/board_enable.c @@ -77,48 +77,48 @@ static int enable_flash_decode_superio(void) case SUPERIO_VENDOR_NONE: ret = -1; break; case SUPERIO_VENDOR_ITE: enter_conf_mode_ite(superio.port); /* Enable flash mapping. Works for most old ITE style Super I/O. */ tmp = sio_read(superio.port, 0x24); tmp |= 0xfc; sio_write(superio.port, 0x24, tmp); exit_conf_mode_ite(superio.port); ret = 0; break; default: - printf_debug("Unhandled Super I/O type!\n"); + msg_perr("Unhandled Super I/O type!\n"); ret = -1; break; } return ret; } #endif /** * Winbond W83627HF: Raise GPIO24. * * Suited for: * - Agami Aruma * - IWILL DK8-HTX */ static int w83627hf_gpio24_raise(uint16_t port, const char *name) { w836xx_ext_enter(port); /* Is this the W83627HF? */ if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */ - fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n", + msg_perr("\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n", name, sio_read(port, 0x20)); w836xx_ext_leave(port); return -1; } /* PIN89S: WDTO/GP24 multiplex -> GPIO24 */ sio_mask(port, 0x2B, 0x10, 0x10); /* Select logical device 8: GPIO port 2 */ sio_write(port, 0x07, 0x08); sio_mask(port, 0x30, 0x01, 0x01); /* Activate logical device. */ sio_mask(port, 0xF0, 0x00, 0x10); /* GPIO24 -> output */ @@ -138,27 +138,27 @@ static int w83627hf_gpio24_raise_2e(const char *name) /** * Winbond W83627THF: GPIO 4, bit 4 * * Suited for: * - MSI K8T Neo2-F * - MSI K8N-NEO3 */ static int w83627thf_gpio4_4_raise(uint16_t port, const char *name) { w836xx_ext_enter(port); /* Is this the W83627THF? */ if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */ - fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n", + msg_perr("\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n", name, sio_read(port, 0x20)); w836xx_ext_leave(port); return -1; } /* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */ sio_write(port, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */ sio_mask(port, 0x30, 0x02, 0x02); /* Activate logical device. */ sio_mask(port, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */ sio_mask(port, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */ sio_mask(port, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */ @@ -243,40 +243,40 @@ static int it8705f_write_enable_2e(const char *name) { return it8705f_write_enable(0x2e, name); } static int pc87360_gpio_set(uint8_t gpio, int raise) { static const int bankbase[] = {0, 4, 8, 10, 12}; int gpio_bank = gpio / 8; int gpio_pin = gpio % 8; uint16_t baseport; uint8_t id, val; if (gpio_bank > 4) { - fprintf(stderr, "PC87360: Invalid GPIO %d\n", gpio); + msg_perr("PC87360: Invalid GPIO %d\n", gpio); return -1; } id = sio_read(0x2E, 0x20); if (id != 0xE1) { - fprintf(stderr, "PC87360: unexpected ID %02x\n", id); + msg_perr("PC87360: unexpected ID %02x\n", id); return -1; } sio_write(0x2E, 0x07, 0x07); /* Select GPIO device */ baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) { - fprintf (stderr, "PC87360: invalid GPIO base address %04x\n", + msg_perr("PC87360: invalid GPIO base address %04x\n", baseport); return -1; } sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device */ sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin); sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output */ val = INB(baseport + bankbase[gpio_bank]); if (raise) val |= 1 << gpio_pin; else val &= ~(1 << gpio_pin); OUTB(val, baseport + bankbase[gpio_bank]); @@ -290,46 +290,46 @@ static int pc87360_gpio_set(uint8_t gpio, int raise) static int via_vt823x_gpio_set(uint8_t gpio, int raise) { struct pci_dev *dev; uint16_t base; uint8_t val, bit, offset; dev = pci_dev_find_vendorclass(0x1106, 0x0601); switch (dev->device_id) { case 0x3177: /* VT8235 */ case 0x3227: /* VT8237R */ case 0x3337: /* VT8237A */ break; default: - fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); + msg_perr("\nERROR: VT823x ISA bridge not found.\n"); return -1; } if ((gpio >= 12) && (gpio <= 15)) { /* GPIO12-15 -> output */ val = pci_read_byte(dev, 0xE4); val |= 0x10; pci_write_byte(dev, 0xE4, val); } else if (gpio == 9) { /* GPIO9 -> Output */ val = pci_read_byte(dev, 0xE4); val |= 0x20; pci_write_byte(dev, 0xE4, val); } else if (gpio == 5) { val = pci_read_byte(dev, 0xE4); val |= 0x01; pci_write_byte(dev, 0xE4, val); } else { - fprintf(stderr, "\nERROR: " + msg_perr("\nERROR: " "VT823x GPIO%02d is not implemented.\n", gpio); return -1; } /* We need the I/O Base Address for this board's flash enable. */ base = pci_read_word(dev, 0x88) & 0xff80; offset = 0x4C + gpio / 8; bit = 0x01 << (gpio % 8); val = INB(base + offset); if (raise) val |= bit; @@ -401,70 +401,70 @@ static int board_asus_p5a(const char *name) OUTB(0x00, 0xE807); OUTB(0xEF, 0xE803); OUTB(0xFF, 0xE800); for (i = 0; i < ASUSP5A_LOOP; i++) { OUTB(0xE1, 0xFF); if (INB(0xE800) & 0x04) break; } if (i == ASUSP5A_LOOP) { - printf("%s: Unable to contact device.\n", name); + msg_perr("%s: Unable to contact device.\n", name); return -1; } OUTB(0x20, 0xE801); OUTB(0x20, 0xE1); OUTB(0xFF, 0xE802); for (i = 0; i < ASUSP5A_LOOP; i++) { tmp = INB(0xE800); if (tmp & 0x70) break; } if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) { - printf("%s: failed to read device.\n", name); + msg_perr("%s: failed to read device.\n", name); return -1; } tmp = INB(0xE804); tmp &= ~0x02; OUTB(0x00, 0xE807); OUTB(0xEE, 0xE803); OUTB(tmp, 0xE804); OUTB(0xFF, 0xE800); OUTB(0xE1, 0xFF); OUTB(0x20, 0xE801); OUTB(0x20, 0xE1); OUTB(0xFF, 0xE802); for (i = 0; i < ASUSP5A_LOOP; i++) { tmp = INB(0xE800); if (tmp & 0x70) break; } if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) { - printf("%s: failed to write to device.\n", name); + msg_perr("%s: failed to write to device.\n", name); return -1; } return 0; } /* * Set GPIO lines in the Broadcom HT-1000 southbridge. * * It's not a Super I/O but it uses the same index/data port method. */ static int board_hp_dl145_g3_enable(const char *name) { @@ -482,67 +482,65 @@ static int board_ibm_x3455(const char *name) return 0; } /** * Suited for Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4). */ static int board_shuttle_fn25(const char *name) { struct pci_dev *dev; dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */ if (!dev) { - fprintf(stderr, - "\nERROR: NVIDIA nForce4 ISA bridge not found.\n"); + msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n"); return -1; } /* one of those bits seems to be connected to TBL#, but -ENOINFO. */ pci_write_byte(dev, 0x92, 0); return 0; } /** * Very similar to AMD 8111 IO Hub. */ static int nvidia_mcp_gpio_set(int gpio, int raise) { struct pci_dev *dev; uint16_t base; uint8_t tmp; if ((gpio < 0) || (gpio >= 0x40)) { - fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio); + msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio); return -1; } /* First, check the ISA Bridge */ dev = pci_dev_find_vendorclass(0x10DE, 0x0601); switch (dev->device_id) { case 0x0030: /* CK804 */ case 0x0050: /* MCP04 */ case 0x0060: /* MCP2 */ break; default: /* Newer MCPs use the SMBus Controller */ dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); switch (dev->device_id) { case 0x0264: /* MCP51 */ break; default: - fprintf(stderr, - "\nERROR: no NVIDIA LPC/SMBus controller found.\n"); + msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n"); return -1; } break; } base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ base += 0xC0; tmp = INB(base + gpio); tmp &= ~0x0F; /* null lower nibble */ tmp |= 0x04; /* gpio -> output. */ if (raise) tmp |= 0x01; @@ -643,40 +641,40 @@ static int board_artecgroup_dbe6x(const char *name) } /** * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}. */ static int intel_piix4_gpo_set(unsigned int gpo, int raise) { unsigned int gpo_byte, gpo_bit; struct pci_dev *dev; uint32_t tmp, base; dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */ if (!dev) { - fprintf(stderr, "\nERROR: Intel PIIX4 ISA bridge not found.\n"); + msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n"); return -1; } /* sanity check */ if (gpo > 30) { - fprintf(stderr, "\nERROR: Intel PIIX4 has no GPO%d.\n", gpo); + msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo); return -1; } /* these are dual function pins which are most likely in use already */ if (((gpo >= 1) && (gpo <= 7)) || ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) { - fprintf(stderr, "\nERROR: Unsupported PIIX4 GPO%d.\n", gpo); + msg_perr("\nERROR: Unsupported PIIX4 GPO%d.\n", gpo); return -1; } /* dual function that need special enable. */ if ((gpo >= 22) && (gpo <= 26)) { tmp = pci_read_long(dev, 0xB0); /* GENCFG */ switch (gpo) { case 22: /* XBUS: XDIR#/GPO22 */ case 23: /* XBUS: XOE#/GPO23 */ tmp |= 1 << 28; break; case 24: /* RTCSS#/GPO24 */ tmp |= 1 << 29; @@ -685,27 +683,27 @@ static int intel_piix4_gpo_set(unsigned int gpo, int raise) tmp |= 1 << 30; break; case 26: /* KBCSS#/GPO26 */ tmp |= 1 << 31; break; } pci_write_long(dev, 0xB0, tmp); } /* GPO {0,8,27,28,30} are always available. */ dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */ if (!dev) { - fprintf(stderr, "\nERROR: Intel PIIX4 PM not found.\n"); + msg_perr("\nERROR: Intel PIIX4 PM not found.\n"); return -1; } /* PM IO base */ base = pci_read_long(dev, 0x40) & 0x0000FFC0; gpo_byte = gpo >> 3; gpo_bit = gpo & 7; tmp = INB(base + 0x34 + gpo_byte); /* GPO register */ if (raise) tmp |= 0x01 << gpo_bit; else tmp &= ~(0x01 << gpo_bit); @@ -787,69 +785,69 @@ static int intel_ich_gpio_set(int gpio, int raise) if ((dev->vendor_id == 0x8086) && (dev->device_class == 0x0601)) { /* ISA Bridge */ /* Is this device in our list? */ for (i = 0; intel_ich_gpio_table[i].id; i++) if (dev->device_id == intel_ich_gpio_table[i].id) break; if (intel_ich_gpio_table[i].id) break; } } if (!dev) { - fprintf(stderr, "\nERROR: No Known Intel LPC Bridge found.\n"); + msg_perr("\nERROR: No Known Intel LPC Bridge found.\n"); return -1; } /* According to the datasheets, all Intel ICHs have the GPIO bar 5:1 strapped to zero. From some mobile ICH9 version on, this becomes 6:1. The mask below catches all. */ base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0; /* check whether the line is allowed */ if (gpio < 32) allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01; else if (gpio < 64) allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01; else allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01; if (!allowed) { - fprintf(stderr, "\nERROR: This Intel LPC Bridge does not allow" + msg_perr("\nERROR: This Intel LPC Bridge does not allow" " setting GPIO%02d\n", gpio); return -1; } - printf("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n", + msg_pdbg("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n", raise ? "Rais" : "Dropp", gpio); if (gpio < 32) { /* Set line to GPIO */ tmp = INL(base); /* ICH/ICH0 multiplexes 27/28 on the line set. */ if ((gpio == 28) && ((dev->device_id == 0x2410) || (dev->device_id == 0x2420))) tmp |= 1 << 27; else tmp |= 1 << gpio; OUTL(tmp, base); /* As soon as we are talking to ICH8 and above, this register decides whether we can set the gpio or not. */ if (dev->device_id > 0x2800) { tmp = INL(base); if (!(tmp & (1 << gpio))) { - fprintf(stderr, "\nERROR: This Intel LPC Bridge" + msg_perr("\nERROR: This Intel LPC Bridge" " does not allow setting GPIO%02d\n", gpio); return -1; } } /* Set GPIO to OUTPUT */ tmp = INL(base + 0x04); tmp &= ~(1 << gpio); OUTL(tmp, base + 0x04); /* Raise GPIO line */ tmp = INL(base + 0x0C); @@ -861,27 +859,27 @@ static int intel_ich_gpio_set(int gpio, int raise) } else if (gpio < 64) { gpio -= 32; /* Set line to GPIO */ tmp = INL(base + 0x30); tmp |= 1 << gpio; OUTL(tmp, base + 0x30); /* As soon as we are talking to ICH8 and above, this register decides whether we can set the gpio or not. */ if (dev->device_id > 0x2800) { tmp = INL(base + 30); if (!(tmp & (1 << gpio))) { - fprintf(stderr, "\nERROR: This Intel LPC Bridge" + msg_perr("\nERROR: This Intel LPC Bridge" " does not allow setting GPIO%02d\n", gpio + 32); return -1; } } /* Set GPIO to OUTPUT */ tmp = INL(base + 0x34); tmp &= ~(1 << gpio); OUTL(tmp, base + 0x34); /* Raise GPIO line */ tmp = INL(base + 0x38); @@ -890,27 +888,27 @@ static int intel_ich_gpio_set(int gpio, int raise) else tmp &= ~(1 << gpio); OUTL(tmp, base + 0x38); } else { gpio -= 64; /* Set line to GPIO */ tmp = INL(base + 0x40); tmp |= 1 << gpio; OUTL(tmp, base + 0x40); tmp = INL(base + 40); if (!(tmp & (1 << gpio))) { - fprintf(stderr, "\nERROR: This Intel LPC Bridge does " + msg_perr("\nERROR: This Intel LPC Bridge does " "not allow setting GPIO%02d\n", gpio + 64); return -1; } /* Set GPIO to OUTPUT */ tmp = INL(base + 0x44); tmp &= ~(1 << gpio); OUTL(tmp, base + 0x44); /* Raise GPIO line */ tmp = INL(base + 0x48); if (raise) tmp |= 1 << gpio; @@ -1033,31 +1031,31 @@ static int board_kontron_986lcd_m(const char *name) /** * Suited for Soyo SY-7VCA: Pro133A + VT82C686. */ static int via_apollo_gpo_set(int gpio, int raise) { struct pci_dev *dev; uint32_t base; uint32_t tmp; /* VT82C686 Power management */ dev = pci_dev_find(0x1106, 0x3057); if (!dev) { - fprintf(stderr, "\nERROR: VT82C686 PM device not found.\n"); + msg_perr("\nERROR: VT82C686 PM device not found.\n"); return -1; } - printf("\nVIA Apollo ACPI: %sing GPIO%02d.\n", + msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n", raise ? "Rais" : "Dropp", gpio); /* select GPO function on multiplexed pins */ tmp = pci_read_byte(dev, 0x54); switch(gpio) { case 0: tmp &= ~0x03; break; case 1: tmp |= 0x04; break; case 2: @@ -1100,27 +1098,27 @@ static int via_apollo_gpo0_lower(const char *name) } /** * Enable some GPIO pin on SiS southbridge. * Suited for MSI 651M-L: SiS651 / SiS962 */ static int board_msi_651ml(const char *name) { struct pci_dev *dev; uint16_t base, temp; dev = pci_dev_find(0x1039, 0x0962); if (!dev) { - fprintf(stderr, "Expected south bridge not found\n"); + msg_perr("Expected south bridge not found\n"); return 1; } /* Registers 68 and 64 seem like bitmaps */ base = pci_read_word(dev, 0x74); temp = INW(base + 0x68); temp &= ~(1 << 0); /* Make pin output? */ OUTW(temp, base + 0x68); temp = INW(base + 0x64); temp |= (1 << 0); /* Raise output? */ OUTW(temp, base + 0x64); @@ -1133,59 +1131,59 @@ static int board_msi_651ml(const char *name) * Find the runtime registers of an SMSC Super I/O, after verifying its * chip ID. * * Returns the base port of the runtime register block, or 0 on error. */ static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id, uint8_t logical_device) { uint16_t rt_port = 0; /* Verify the chip ID. */ OUTB(0x55, sio_port); /* Enable configuration. */ if (sio_read(sio_port, 0x20) != chip_id) { - fprintf(stderr, "\nERROR: SMSC Super I/O not found.\n"); + msg_perr("\nERROR: SMSC Super I/O not found.\n"); goto out; } /* If the runtime block is active, get its address. */ sio_write(sio_port, 0x07, logical_device); if (sio_read(sio_port, 0x30) & 1) { rt_port = (sio_read(sio_port, 0x60) << 8) | sio_read(sio_port, 0x61); } if (rt_port == 0) { - fprintf(stderr, "\nERROR: " + msg_perr("\nERROR: " "Super I/O runtime interface not available.\n"); } out: OUTB(0xaa, sio_port); /* Disable configuration. */ return rt_port; } /** * Disable write protection on the Mitac 6513WU. WP# on the FWH is * connected to GP30 on the Super I/O, and TBL# is always high. */ static int board_mitac_6513wu(const char *name) { struct pci_dev *dev; uint16_t rt_port; uint8_t val; dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */ if (!dev) { - fprintf(stderr, "\nERROR: Intel 82801AA ISA bridge not found.\n"); + msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n"); return -1; } rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa); if (rt_port == 0) return -1; /* Configure the GPIO pin. */ val = INB(rt_port + 0x33); /* GP30 config */ val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */ OUTB(val, rt_port + 0x33); /* Disable write protection. */ @@ -1200,38 +1198,38 @@ static int board_mitac_6513wu(const char *name) * Suited for ASUS A7V8X: VIA KT400 + VT8235 + IT8703F-A */ static int board_asus_a7v8x(const char *name) { uint16_t id, base; uint8_t tmp; /* find the IT8703F */ w836xx_ext_enter(0x2E); id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); w836xx_ext_leave(0x2E); if (id != 0x8701) { - fprintf(stderr, "\nERROR: IT8703F Super I/O not found.\n"); + msg_perr("\nERROR: IT8703F Super I/O not found.\n"); return -1; } /* Get the GP567 IO base */ w836xx_ext_enter(0x2E); sio_write(0x2E, 0x07, 0x0C); base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); w836xx_ext_leave(0x2E); if (!base) { - fprintf(stderr, "\nERROR: Failed to read IT8703F Super I/O GPIO" + msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO" " Base.\n"); return -1; } /* Raise GP51. */ tmp = INB(base); tmp |= 0x02; OUTB(tmp, base); return 0; } /* @@ -1241,49 +1239,48 @@ static int board_asus_a7v8x(const char *name) static int it8712f_gpio_set(unsigned int line, int raise) { unsigned int port; uint16_t id, base; uint8_t tmp; port = line / 10; port--; line %= 10; /* Check line */ if ((port > 4) || /* also catches unsigned -1 */ ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) { - fprintf(stderr, - "\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line); + msg_perr("\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line); return -1; } /* find the IT8712F */ enter_conf_mode_ite(0x2E); id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); exit_conf_mode_ite(0x2E); if (id != 0x8712) { - fprintf(stderr, "\nERROR: IT8712F Super I/O not found.\n"); + msg_perr("\nERROR: IT8712F Super I/O not found.\n"); return -1; } /* Get the GPIO base */ enter_conf_mode_ite(0x2E); sio_write(0x2E, 0x07, 0x07); base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63); exit_conf_mode_ite(0x2E); if (!base) { - fprintf(stderr, "\nERROR: Failed to read IT8712F Super I/O GPIO" + msg_perr("\nERROR: Failed to read IT8712F Super I/O GPIO" " Base.\n"); return -1; } /* set GPIO. */ tmp = INB(base + port); if (raise) tmp |= 1 << line; else tmp &= ~(1 << line); OUTB(tmp, base + port); return 0; @@ -1431,44 +1428,44 @@ static struct board_pciid_enable *board_match_coreboot_name(const char *vendor, if (!pci_dev_find(board->first_vendor, board->first_device)) continue; if (board->second_vendor && !pci_dev_find(board->second_vendor, board->second_device)) continue; if (vendor) return board; if (partmatch) { /* a second entry has a matching part name */ - printf("AMBIGUOUS BOARD NAME: %s\n", part); - printf("At least vendors '%s' and '%s' match.\n", + msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part); + msg_pinfo("At least vendors '%s' and '%s' match.\n", partmatch->lb_vendor, board->lb_vendor); - printf("Please use the full -m vendor:part syntax.\n"); + msg_pinfo("Please use the full -m vendor:part syntax.\n"); return NULL; } partmatch = board; } if (partmatch) return partmatch; if (!partvendor_from_cbtable) { /* Only warn if the mainboard type was not gathered from the * coreboot table. If it was, the coreboot implementor is * expected to fix flashrom, too. */ - printf("\nUnknown vendor:board from -m option: %s:%s\n\n", + msg_pinfo("\nUnknown vendor:board from -m option: %s:%s\n\n", vendor, part); } return NULL; } /** * Match boards on PCI IDs and subsystem IDs. * Second set of IDs can be main only or missing completely. */ static struct board_pciid_enable *board_match_pci_card_ids(void) { struct board_pciid_enable *board = board_pciid_enables; @@ -1488,27 +1485,27 @@ static struct board_pciid_enable *board_match_pci_card_ids(void) board->second_device, board->second_card_vendor, board->second_card_device)) continue; } else { if (!pci_dev_find(board->second_vendor, board->second_device)) continue; } } if (board->dmi_pattern) { if (!has_dmi_support) { - fprintf(stderr, "WARNING: Can't autodetect %s %s," + msg_perr("WARNING: Can't autodetect %s %s," " DMI info unavailable.\n", board->vendor_name, board->board_name); continue; } else { if (!dmi_match(board->dmi_pattern)) continue; } } return board; } return NULL; @@ -1517,47 +1514,47 @@ static struct board_pciid_enable *board_match_pci_card_ids(void) int board_flash_enable(const char *vendor, const char *part) { struct board_pciid_enable *board = NULL; int ret = 0; if (part) board = board_match_coreboot_name(vendor, part); if (!board) board = board_match_pci_card_ids(); if (board && board->status == NT) { if (!force_boardenable) { - printf("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" + msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" "code has not been tested, and thus will not not be executed by default.\n" "Depending on your hardware environment, erasing, writing or even probing\n" "can fail without running the board specific code.\n\n" "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n" "\"internal programmer\") for details.\n", board->vendor_name, board->board_name); board = NULL; } else { - printf("NOTE: Running an untested board enable procedure.\n" + msg_pinfo("NOTE: Running an untested board enable procedure.\n" "Please report success/failure to flashrom(a)flashrom.org.\n"); } } if (board) { if (board->max_rom_decode_parallel) max_rom_decode.parallel = board->max_rom_decode_parallel * 1024; if (board->enable != NULL) { - printf("Disabling flash write protection for " + msg_pinfo("Disabling flash write protection for " "board \"%s %s\"... ", board->vendor_name, board->board_name); ret = board->enable(board->vendor_name); if (ret) - printf("FAILED!\n"); + msg_pinfo("FAILED!\n"); else - printf("OK.\n"); + msg_pinfo("OK.\n"); } } return ret; } diff --git a/cbtable.c b/cbtable.c index c12354c..ce74381 100644 --- a/cbtable.c +++ b/cbtable.c @@ -102,76 +102,76 @@ static int count_lb_records(struct lb_header *head) static struct lb_header *find_lb_table(void *base, unsigned long start, unsigned long end) { unsigned long addr; /* For now be stupid.... */ for (addr = start; addr < end; addr += 16) { struct lb_header *head = (struct lb_header *)(((char *)base) + addr); struct lb_record *recs = (struct lb_record *)(((char *)base) + addr + sizeof(*head)); if (memcmp(head->signature, "LBIO", 4) != 0) continue; - printf_debug("Found candidate at: %08lx-%08lx\n", + msg_pdbg("Found candidate at: %08lx-%08lx\n", addr, addr + head->table_bytes); if (head->header_bytes != sizeof(*head)) { - fprintf(stderr, "Header bytes of %d are incorrect.\n", + msg_pdbg("Header bytes of %d are incorrect.\n", head->header_bytes); continue; } if (count_lb_records(head) != head->table_entries) { - fprintf(stderr, "Bad record count: %d.\n", + msg_pdbg("Bad record count: %d.\n", head->table_entries); continue; } if (compute_checksum((uint8_t *) head, sizeof(*head)) != 0) { - fprintf(stderr, "Bad header checksum.\n"); + msg_pdbg("Bad header checksum.\n"); continue; } if (compute_checksum(recs, head->table_bytes) != head->table_checksum) { - fprintf(stderr, "Bad table checksum: %04x.\n", + msg_pdbg("Bad table checksum: %04x.\n", head->table_checksum); continue; } - printf_debug("Found coreboot table at 0x%08lx.\n", addr); + msg_pdbg("Found coreboot table at 0x%08lx.\n", addr); return head; }; return 0; } static void find_mainboard(struct lb_record *ptr, unsigned long addr) { struct lb_mainboard *rec; int max_size; char vendor[256], part[256]; rec = (struct lb_mainboard *)ptr; max_size = rec->size - sizeof(*rec); - printf("Vendor ID: %.*s, part ID: %.*s\n", + msg_pdbg("Vendor ID: %.*s, part ID: %.*s\n", max_size - rec->vendor_idx, rec->strings + rec->vendor_idx, max_size - rec->part_number_idx, rec->strings + rec->part_number_idx); snprintf(vendor, 255, "%.*s", max_size - rec->vendor_idx, rec->strings + rec->vendor_idx); snprintf(part, 255, "%.*s", max_size - rec->part_number_idx, rec->strings + rec->part_number_idx); if (lb_part) { - printf("Overwritten by command line, vendor ID: %s, part ID: %s.\n", lb_vendor, lb_part); + msg_pdbg("Overwritten by command line, vendor ID: %s, part ID: %s.\n", lb_vendor, lb_part); } else { partvendor_from_cbtable = 1; lb_part = strdup(part); lb_vendor = strdup(vendor); } } static struct lb_record *next_record(struct lb_record *rec) { return (struct lb_record *)(((char *)rec) + rec->size); } static void search_lb_records(struct lb_record *rec, struct lb_record *last, @@ -200,55 +200,55 @@ int coreboot_init(void) struct lb_header *lb_table; struct lb_record *rec, *last; #ifdef __DARWIN__ /* This is a hack. DirectIO fails to map physical address 0x00000000. * Why? */ start = 0x400; #else start = 0x0; #endif table_area = physmap_try_ro("low megabyte", start, BYTES_TO_MAP - start); if (!table_area) { - msg_perr("Failed getting access to coreboot low tables.\n"); + msg_pdbg("Failed getting access to coreboot low tables.\n"); return -1; } lb_table = find_lb_table(table_area, 0x00000, 0x1000); if (!lb_table) lb_table = find_lb_table(table_area, 0xf0000 - start, BYTES_TO_MAP - start); if (lb_table) { struct lb_forward *forward = (struct lb_forward *) (((char *)lb_table) + lb_table->header_bytes); if (forward->tag == LB_TAG_FORWARD) { start = forward->forward; start &= ~(getpagesize() - 1); physunmap(table_area, BYTES_TO_MAP); table_area = physmap_try_ro("high tables", start, BYTES_TO_MAP); if (!table_area) { - msg_perr("Failed getting access to coreboot " + msg_pdbg("Failed getting access to coreboot " "high tables.\n"); return -1; } lb_table = find_lb_table(table_area, 0x00000, 0x1000); } } if (!lb_table) { - printf("No coreboot table found.\n"); + msg_pinfo("No coreboot table found.\n"); return -1; } addr = ((char *)lb_table) - ((char *)table_area) + start; - fprintf(stdout, "coreboot table found at 0x%lx.\n", + msg_pinfo("coreboot table found at 0x%lx.\n", (unsigned long)lb_table - (unsigned long)table_area + start); rec = (struct lb_record *)(((char *)lb_table) + lb_table->header_bytes); last = (struct lb_record *)(((char *)rec) + lb_table->table_bytes); - printf_debug("coreboot header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n", + msg_pdbg("coreboot header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n", lb_table->header_bytes, lb_table->header_checksum, lb_table->table_bytes, lb_table->table_checksum, lb_table->table_entries); search_lb_records(rec, last, addr + lb_table->header_bytes); return 0; } diff --git a/chipset_enable.c b/chipset_enable.c index fc60484..f447685 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -64,46 +64,46 @@ static int enable_flash_sis85c496(struct pci_dev *dev, const char *name) static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name) { uint8_t new, newer; /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */ /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */ new = pci_read_byte(dev, 0x40); new &= (~0x04); /* No idea why we clear bit 2. */ new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */ pci_write_byte(dev, 0x40, new); newer = pci_read_byte(dev, 0x40); if (newer != new) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); - printf_debug("Stuck at 0x%x\n", newer); + msg_pdbg("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); + msg_pdbg("Stuck at 0x%x\n", newer); return -1; } return 0; } static struct pci_dev *find_southbridge(uint16_t vendor, const char *name) { struct pci_dev *sbdev; sbdev = pci_dev_find_vendorclass(vendor, 0x0601); if (!sbdev) sbdev = pci_dev_find_vendorclass(vendor, 0x0680); if (!sbdev) sbdev = pci_dev_find_vendorclass(vendor, 0x0000); if (!sbdev) - fprintf(stderr, "No southbridge found for %s!\n", name); + msg_perr("No southbridge found for %s!\n", name); if (sbdev) - printf_debug("Found southbridge %04x:%04x at %02x:%02x:%01x\n", + msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n", sbdev->vendor_id, sbdev->device_id, sbdev->bus, sbdev->dev, sbdev->func); return sbdev; } static int enable_flash_sis501(struct pci_dev *dev, const char *name) { uint8_t tmp; int ret = 0; struct pci_dev *sbdev; sbdev = find_southbridge(dev->vendor_id, name); if (!sbdev) @@ -152,54 +152,54 @@ static int enable_flash_sis530(struct pci_dev *dev, const char *name) sbdev = find_southbridge(dev->vendor_id, name); if (!sbdev) return -1; ret = enable_flash_sis_mapping(sbdev, name); new = pci_read_byte(sbdev, 0x45); new &= (~0x20); new |= 0x4; pci_write_byte(sbdev, 0x45, new); newer = pci_read_byte(sbdev, 0x45); if (newer != new) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); - printf_debug("Stuck at 0x%x\n", newer); + msg_pdbg("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); + msg_pdbg("Stuck at 0x%x\n", newer); ret = -1; } return ret; } static int enable_flash_sis540(struct pci_dev *dev, const char *name) { uint8_t new, newer; int ret = 0; struct pci_dev *sbdev; sbdev = find_southbridge(dev->vendor_id, name); if (!sbdev) return -1; ret = enable_flash_sis_mapping(sbdev, name); new = pci_read_byte(sbdev, 0x45); new &= (~0x80); new |= 0x40; pci_write_byte(sbdev, 0x45, new); newer = pci_read_byte(sbdev, 0x45); if (newer != new) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); - printf_debug("Stuck at 0x%x\n", newer); + msg_pdbg("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); + msg_pdbg("Stuck at 0x%x\n", newer); ret = -1; } return ret; } /* Datasheet: * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) * - URL: http://www.intel.com/design/intarch/datashts/290562.htm * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf * - Order Number: 290562-001 */ static int enable_flash_piix4(struct pci_dev *dev, const char *name) @@ -225,63 +225,63 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name) */ if (dev->device_id == 0x122e || dev->device_id == 0x7000 || dev->device_id == 0x1234) new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */ else new = old | 0x02c4; if (new == old) return 0; pci_write_word(dev, xbcs, new); if (pci_read_word(dev, xbcs) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name); + msg_pdbg("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name); return -1; } return 0; } /* * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet" * http://download.intel.com/design/chipsets/datashts/30701303.pdf */ static int enable_flash_ich(struct pci_dev *dev, const char *name, int bios_cntl) { uint8_t old, new; /* * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but * just treating it as 8 bit wide seems to work fine in practice. */ old = pci_read_byte(dev, bios_cntl); - printf_debug("\nBIOS Lock Enable: %sabled, ", + msg_pdbg("\nBIOS Lock Enable: %sabled, ", (old & (1 << 1)) ? "en" : "dis"); - printf_debug("BIOS Write Enable: %sabled, ", + msg_pdbg("BIOS Write Enable: %sabled, ", (old & (1 << 0)) ? "en" : "dis"); - printf_debug("BIOS_CNTL is 0x%x\n", old); + msg_pdbg("BIOS_CNTL is 0x%x\n", old); new = old | 1; if (new == old) return 0; pci_write_byte(dev, bios_cntl, new); if (pci_read_byte(dev, bios_cntl) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name); + msg_pdbg("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name); return -1; } return 0; } static int enable_flash_ich_4e(struct pci_dev *dev, const char *name) { /* * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and * FB_DEC_EN2. */ @@ -296,137 +296,137 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) int tmp; int max_decode_fwh_idsel = 0; int max_decode_fwh_decode = 0; int contiguous = 1; if (programmer_param) idsel = strstr(programmer_param, "fwh_idsel="); if (idsel) { idsel += strlen("fwh_idsel="); fwh_conf = (uint32_t)strtoul(idsel, NULL, 0); /* FIXME: Need to undo this on shutdown. */ - printf("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf); + msg_pdbg("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf); pci_write_long(dev, 0xd0, fwh_conf); pci_write_word(dev, 0xd4, fwh_conf); /* FIXME: Decode settings are not changed. */ } /* Ignore all legacy ranges below 1 MB. * We currently only support flashing the chip which responds to * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations * have to be adjusted. */ /* FWH_SEL1 */ fwh_conf = pci_read_long(dev, 0xd0); for (i = 7; i >= 0; i--) { tmp = (fwh_conf >> (i * 4)) & 0xf; - printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x", + msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x", (0x1ff8 + i) * 0x80000, (0x1ff0 + i) * 0x80000, tmp); if ((tmp == 0) && contiguous) { max_decode_fwh_idsel = (8 - i) * 0x80000; } else { contiguous = 0; } } /* FWH_SEL2 */ fwh_conf = pci_read_word(dev, 0xd4); for (i = 3; i >= 0; i--) { tmp = (fwh_conf >> (i * 4)) & 0xf; - printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x", + msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x", (0xff4 + i) * 0x100000, (0xff0 + i) * 0x100000, tmp); if ((tmp == 0) && contiguous) { max_decode_fwh_idsel = (8 - i) * 0x100000; } else { contiguous = 0; } } contiguous = 1; /* FWH_DEC_EN1 */ fwh_conf = pci_read_word(dev, 0xd8); for (i = 7; i >= 0; i--) { tmp = (fwh_conf >> (i + 0x8)) & 0x1; - printf_debug("\n0x%08x/0x%08x FWH decode %sabled", + msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled", (0x1ff8 + i) * 0x80000, (0x1ff0 + i) * 0x80000, tmp ? "en" : "dis"); if ((tmp == 1) && contiguous) { max_decode_fwh_decode = (8 - i) * 0x80000; } else { contiguous = 0; } } for (i = 3; i >= 0; i--) { tmp = (fwh_conf >> i) & 0x1; - printf_debug("\n0x%08x/0x%08x FWH decode %sabled", + msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled", (0xff4 + i) * 0x100000, (0xff0 + i) * 0x100000, tmp ? "en" : "dis"); if ((tmp == 1) && contiguous) { max_decode_fwh_decode = (8 - i) * 0x100000; } else { contiguous = 0; } } max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); - printf_debug("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); + msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); /* If we're called by enable_flash_ich_dc_spi, it will override * buses_supported anyway. */ buses_supported = CHIP_BUSTYPE_FWH; return enable_flash_ich(dev, name, 0xdc); } static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) { uint16_t old, new; int err; if ((err = enable_flash_ich(dev, name, 0xd8)) != 0) return err; old = pci_read_byte(dev, 0xd9); - printf_debug("BIOS Prefetch Enable: %sabled, ", + msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis"); new = old & ~1; if (new != old) pci_write_byte(dev, 0xd9, new); return 0; } #define ICH_STRAP_RSVD 0x00 #define ICH_STRAP_SPI 0x01 #define ICH_STRAP_PCI 0x02 #define ICH_STRAP_LPC 0x03 static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) { uint32_t mmio_base; /* Do we really need no write enable? */ mmio_base = (pci_read_long(dev, 0xbc)) << 8; - printf_debug("MMIO base at = 0x%x\n", mmio_base); + msg_pdbg("MMIO base at = 0x%x\n", mmio_base); spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); - printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", + msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", mmio_readw(spibar + 0x6c)); /* Not sure if it speaks all these bus protocols. */ buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_VIA; ich_init_opcodes(); return 0; } static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, int ich_generation) { @@ -434,40 +434,40 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, uint8_t old, new, bbs, buc; uint16_t spibar_offset, tmp2; uint32_t tmp, gcs; void *rcrb; //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" }; static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" }; /* Enable Flash Writes */ ret = enable_flash_ich_dc(dev, name); /* Get physical address of Root Complex Register Block */ tmp = pci_read_long(dev, 0xf0) & 0xffffc000; - printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp); + msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp); /* Map RCBA to virtual memory */ rcrb = physmap("ICH RCRB", tmp, 0x4000); gcs = mmio_readl(rcrb + 0x3410); - printf_debug("GCS = 0x%x: ", gcs); - printf_debug("BIOS Interface Lock-Down: %sabled, ", + msg_pdbg("GCS = 0x%x: ", gcs); + msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); bbs = (gcs >> 10) & 0x3; - printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); + msg_pdbg("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); buc = mmio_readb(rcrb + 0x3414); - printf_debug("Top Swap : %s\n", + msg_pdbg("Top Swap : %s\n", (buc & 1) ? "enabled (A16 inverted)" : "not enabled"); /* It seems the ICH7 does not support SPI and LPC chips at the same * time. At least not with our current code. So we prevent searching * on ICH7 when the southbridge is strapped to LPC */ if (ich_generation == 7 && bbs == ICH_STRAP_LPC) { buses_supported = CHIP_BUSTYPE_FWH; /* No further SPI initialization required */ return ret; } @@ -482,147 +482,147 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3800; break; } /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ - printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); + msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); /* Assign Virtual Address */ spibar = rcrb + spibar_offset; switch (spi_controller) { case SPI_CONTROLLER_ICH7: - printf_debug("0x00: 0x%04x (SPIS)\n", + msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(spibar + 0)); - printf_debug("0x02: 0x%04x (SPIC)\n", + msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(spibar + 2)); - printf_debug("0x04: 0x%08x (SPIA)\n", + msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(spibar + 4)); for (i = 0; i < 8; i++) { int offs; offs = 8 + (i * 8); - printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, + msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, mmio_readl(spibar + offs), i); - printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, + msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, mmio_readl(spibar + offs + 4), i); } - printf_debug("0x50: 0x%08x (BBAR)\n", + msg_pdbg("0x50: 0x%08x (BBAR)\n", mmio_readl(spibar + 0x50)); - printf_debug("0x54: 0x%04x (PREOP)\n", + msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(spibar + 0x54)); - printf_debug("0x56: 0x%04x (OPTYPE)\n", + msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(spibar + 0x56)); - printf_debug("0x58: 0x%08x (OPMENU)\n", + msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(spibar + 0x58)); - printf_debug("0x5c: 0x%08x (OPMENU+4)\n", + msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(spibar + 0x5c)); for (i = 0; i < 4; i++) { int offs; offs = 0x60 + (i * 4); - printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, + msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, mmio_readl(spibar + offs), i); } - printf_debug("\n"); + msg_pdbg("\n"); if (mmio_readw(spibar) & (1 << 15)) { - printf("WARNING: SPI Configuration Lockdown activated.\n"); + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } ich_init_opcodes(); break; case SPI_CONTROLLER_ICH9: tmp2 = mmio_readw(spibar + 4); - printf_debug("0x04: 0x%04x (HSFS)\n", tmp2); - printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1)); - printf_debug("FDV %i, ", (tmp2 >> 14) & 1); - printf_debug("FDOPSS %i, ", (tmp2 >> 13) & 1); - printf_debug("SCIP %i, ", (tmp2 >> 5) & 1); - printf_debug("BERASE %i, ", (tmp2 >> 3) & 3); - printf_debug("AEL %i, ", (tmp2 >> 2) & 1); - printf_debug("FCERR %i, ", (tmp2 >> 1) & 1); - printf_debug("FDONE %i\n", (tmp2 >> 0) & 1); + msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); + msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); + msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); + msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); + msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); + msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); + msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); + msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); + msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); tmp = mmio_readl(spibar + 0x50); - printf_debug("0x50: 0x%08x (FRAP)\n", tmp); - printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff); - printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff); - printf_debug("BRWA %i, ", (tmp >> 8) & 0xff); - printf_debug("BRRA %i\n", (tmp >> 0) & 0xff); + msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); + msg_pdbg("BMWAG %i, ", (tmp >> 24) & 0xff); + msg_pdbg("BMRAG %i, ", (tmp >> 16) & 0xff); + msg_pdbg("BRWA %i, ", (tmp >> 8) & 0xff); + msg_pdbg("BRRA %i\n", (tmp >> 0) & 0xff); - printf_debug("0x54: 0x%08x (FREG0)\n", + msg_pdbg("0x54: 0x%08x (FREG0)\n", mmio_readl(spibar + 0x54)); - printf_debug("0x58: 0x%08x (FREG1)\n", + msg_pdbg("0x58: 0x%08x (FREG1)\n", mmio_readl(spibar + 0x58)); - printf_debug("0x5C: 0x%08x (FREG2)\n", + msg_pdbg("0x5C: 0x%08x (FREG2)\n", mmio_readl(spibar + 0x5C)); - printf_debug("0x60: 0x%08x (FREG3)\n", + msg_pdbg("0x60: 0x%08x (FREG3)\n", mmio_readl(spibar + 0x60)); - printf_debug("0x64: 0x%08x (FREG4)\n", + msg_pdbg("0x64: 0x%08x (FREG4)\n", mmio_readl(spibar + 0x64)); - printf_debug("0x74: 0x%08x (PR0)\n", + msg_pdbg("0x74: 0x%08x (PR0)\n", mmio_readl(spibar + 0x74)); - printf_debug("0x78: 0x%08x (PR1)\n", + msg_pdbg("0x78: 0x%08x (PR1)\n", mmio_readl(spibar + 0x78)); - printf_debug("0x7C: 0x%08x (PR2)\n", + msg_pdbg("0x7C: 0x%08x (PR2)\n", mmio_readl(spibar + 0x7C)); - printf_debug("0x80: 0x%08x (PR3)\n", + msg_pdbg("0x80: 0x%08x (PR3)\n", mmio_readl(spibar + 0x80)); - printf_debug("0x84: 0x%08x (PR4)\n", + msg_pdbg("0x84: 0x%08x (PR4)\n", mmio_readl(spibar + 0x84)); - printf_debug("0x90: 0x%08x (SSFS, SSFC)\n", + msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", mmio_readl(spibar + 0x90)); - printf_debug("0x94: 0x%04x (PREOP)\n", + msg_pdbg("0x94: 0x%04x (PREOP)\n", mmio_readw(spibar + 0x94)); - printf_debug("0x96: 0x%04x (OPTYPE)\n", + msg_pdbg("0x96: 0x%04x (OPTYPE)\n", mmio_readw(spibar + 0x96)); - printf_debug("0x98: 0x%08x (OPMENU)\n", + msg_pdbg("0x98: 0x%08x (OPMENU)\n", mmio_readl(spibar + 0x98)); - printf_debug("0x9C: 0x%08x (OPMENU+4)\n", + msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(spibar + 0x9C)); - printf_debug("0xA0: 0x%08x (BBAR)\n", + msg_pdbg("0xA0: 0x%08x (BBAR)\n", mmio_readl(spibar + 0xA0)); - printf_debug("0xB0: 0x%08x (FDOC)\n", + msg_pdbg("0xB0: 0x%08x (FDOC)\n", mmio_readl(spibar + 0xB0)); if (tmp2 & (1 << 15)) { - printf("WARNING: SPI Configuration Lockdown activated.\n"); + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } ich_init_opcodes(); break; default: /* Nothing */ break; } old = pci_read_byte(dev, 0xdc); - printf_debug("SPI Read Configuration: "); + msg_pdbg("SPI Read Configuration: "); new = (old >> 2) & 0x3; switch (new) { case 0: case 1: case 2: - printf_debug("prefetching %sabled, caching %sabled, ", + msg_pdbg("prefetching %sabled, caching %sabled, ", (new & 0x2) ? "en" : "dis", (new & 0x1) ? "dis" : "en"); break; default: - printf_debug("invalid prefetching/caching settings, "); + msg_pdbg("invalid prefetching/caching settings, "); break; } return ret; } static int enable_flash_ich7(struct pci_dev *dev, const char *name) { return enable_flash_ich_dc_spi(dev, name, 7); } static int enable_flash_ich8(struct pci_dev *dev, const char *name) { @@ -642,27 +642,27 @@ static int enable_flash_ich10(struct pci_dev *dev, const char *name) static int enable_flash_vt823x(struct pci_dev *dev, const char *name) { uint8_t val; /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */ pci_write_byte(dev, 0x41, 0x7f); /* ROM write enable */ val = pci_read_byte(dev, 0x40); val |= 0x10; pci_write_byte(dev, 0x40, val); if (pci_read_byte(dev, 0x40) != val) { - printf("\nWARNING: Failed to enable flash write on \"%s\"\n", + msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n", name); return -1; } if (dev->device_id == 0x3227) { /* VT8237R */ /* All memory cycles, not just ROM ones, go to LPC. */ val = pci_read_byte(dev, 0x59); val &= ~0x80; pci_write_byte(dev, 0x59, val); } return 0; } @@ -759,189 +759,189 @@ static int enable_flash_cs5536(struct pci_dev *dev, const char *name) #undef MSR_NORF_CTL return 0; } static int enable_flash_sc1100(struct pci_dev *dev, const char *name) { uint8_t new; pci_write_byte(dev, 0x52, 0xee); new = pci_read_byte(dev, 0x52); if (new != 0xee) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name); + msg_pdbg("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name); return -1; } return 0; } /* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */ static int enable_flash_amd8111(struct pci_dev *dev, const char *name) { uint8_t old, new; /* Enable decoding at 0xffb00000 to 0xffffffff. */ old = pci_read_byte(dev, 0x43); new = old | 0xC0; if (new != old) { pci_write_byte(dev, 0x43, new); if (pci_read_byte(dev, 0x43) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name); + msg_pdbg("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name); } } /* Enable 'ROM write' bit. */ old = pci_read_byte(dev, 0x40); new = old | 0x01; if (new == old) return 0; pci_write_byte(dev, 0x40, new); if (pci_read_byte(dev, 0x40) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); + msg_pdbg("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); return -1; } return 0; } static int enable_flash_sb600(struct pci_dev *dev, const char *name) { uint32_t tmp, prot; uint8_t reg; struct pci_dev *smbus_dev; int has_spi = 1; /* Clear ROM protect 0-3. */ for (reg = 0x50; reg < 0x60; reg += 4) { prot = pci_read_long(dev, reg); /* No protection flags for this region?*/ if ((prot & 0x3) == 0) continue; - printf_debug("SB600 %s%sprotected from %u to %u\n", + msg_pdbg("SB600 %s%sprotected from %u to %u\n", (prot & 0x1) ? "write " : "", (prot & 0x2) ? "read " : "", (prot & 0xfffffc00), (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); prot &= 0xfffffffc; pci_write_byte(dev, reg, prot); prot = pci_read_long(dev, reg); if (prot & 0x3) - printf("SB600 %s%sunprotect failed from %u to %u\n", + msg_pinfo("SB600 %s%sunprotect failed from %u to %u\n", (prot & 0x1) ? "write " : "", (prot & 0x2) ? "read " : "", (prot & 0xfffffc00), (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); } /* Read SPI_BaseAddr */ tmp = pci_read_long(dev, 0xa0); tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ - printf_debug("SPI base address is at 0x%x\n", tmp); + msg_pdbg("SPI base address is at 0x%x\n", tmp); /* If the BAR has address 0, it is unlikely SPI is used. */ if (!tmp) has_spi = 0; if (has_spi) { /* Physical memory has to be mapped at page (4k) boundaries. */ sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); /* The low bits of the SPI base address are used as offset into * the mapped page. */ sb600_spibar += tmp & 0xfff; tmp = pci_read_long(dev, 0xa0); - printf_debug("AltSpiCSEnable=%i, SpiRomEnable=%i, " + msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, (tmp & 0x4) >> 2); tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; - printf_debug("PrefetchEnSPIFromIMC=%i, ", tmp); + msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); tmp = pci_read_byte(dev, 0xbb); - printf_debug("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", + msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", tmp & 0x1, (tmp & 0x20) >> 5); tmp = mmio_readl(sb600_spibar); - printf_debug("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " + msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); } /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); if (has_spi && !smbus_dev) { - fprintf(stderr, "ERROR: SMBus device not found. Not enabling SPI.\n"); + msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); has_spi = 0; } if (has_spi) { /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ reg = pci_read_byte(smbus_dev, 0xAB); reg &= 0xC0; - printf_debug("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); - printf_debug("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); + msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); + msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); if (reg != 0x00) has_spi = 0; /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ reg = pci_read_byte(smbus_dev, 0x83); reg &= 0xC0; - printf_debug("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); - printf_debug("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); + msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); + msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); /* SPI_HOLD is not used on all boards, filter it out. */ if ((reg & 0x80) != 0x00) has_spi = 0; /* GPIO47/SPI_CLK status */ reg = pci_read_byte(smbus_dev, 0xA7); reg &= 0x40; - printf_debug("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); + msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); if (reg != 0x00) has_spi = 0; } buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; if (has_spi) { buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_SB600; } /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); reg = INB(0xcd7); reg &= 0x0e; - printf_debug("ROM strap override is %sactive", (reg & 0x02) ? "" : "not "); + msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not "); if (reg & 0x02) { switch ((reg & 0x0c) >> 2) { case 0x00: - printf_debug(": LPC"); + msg_pdbg(": LPC"); break; case 0x01: - printf_debug(": PCI"); + msg_pdbg(": PCI"); break; case 0x02: - printf_debug(": FWH"); + msg_pdbg(": FWH"); break; case 0x03: - printf_debug(": SPI"); + msg_pdbg(": SPI"); break; } } - printf_debug("\n"); + msg_pdbg("\n"); /* Force enable SPI ROM in SB600 PM register. * If we enable SPI ROM here, we have to disable it after we leave. * But how can we know which ROM we are going to handle? So we have * to trade off. We only access LPC ROM if we boot via LPC ROM. And * only SPI ROM if we boot via SPI ROM. If you want to access SPI on * boards with LPC straps, you have to use the code below. */ /* OUTB(0x8f, 0xcd6); OUTB(0x0e, 0xcd7); */ @@ -960,55 +960,55 @@ static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) return 0; } static int enable_flash_ck804(struct pci_dev *dev, const char *name) { uint8_t old, new; old = pci_read_byte(dev, 0x88); new = old | 0xc0; if (new != old) { pci_write_byte(dev, 0x88, new); if (pci_read_byte(dev, 0x88) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name); + msg_pdbg("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name); } } old = pci_read_byte(dev, 0x6d); new = old | 0x01; if (new == old) return 0; pci_write_byte(dev, 0x6d, new); if (pci_read_byte(dev, 0x6d) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); + msg_pdbg("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); return -1; } return 0; } /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ static int enable_flash_sb400(struct pci_dev *dev, const char *name) { uint8_t tmp; struct pci_dev *smbusdev; /* Look for the SMBus device. */ smbusdev = pci_dev_find(0x1002, 0x4372); if (!smbusdev) { - fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n"); + msg_perr("ERROR: SMBus device not found. Aborting.\n"); exit(1); } /* Enable some SMBus stuff. */ tmp = pci_read_byte(smbusdev, 0x79); tmp |= 0x01; pci_write_byte(smbusdev, 0x79, tmp); /* Change southbridge. */ tmp = pci_read_byte(dev, 0x48); tmp |= 0x21; pci_write_byte(dev, 0x48, tmp); @@ -1037,27 +1037,27 @@ static int enable_flash_mcp55(struct pci_dev *dev, const char *name) val |= 0xff; /* 1M */ pci_write_byte(dev, 0x8c, val); wordval = pci_read_word(dev, 0x90); wordval |= 0x7fff; /* 16M */ pci_write_word(dev, 0x90, wordval); old = pci_read_byte(dev, 0x6d); new = old | 0x01; if (new == old) return 0; pci_write_byte(dev, 0x6d, new); if (pci_read_byte(dev, 0x6d) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); + msg_pdbg("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); return -1; } return 0; } /* This is a shot in the dark. Even if the code is totally bogus for some * chipsets, users will at least start to send in reports. */ static int enable_flash_mcp6x_7x_common(struct pci_dev *dev, const char *name) { int ret = 0; uint8_t val; @@ -1267,27 +1267,27 @@ static int get_flashbase_sc520(struct pci_dev *dev, const char *name) /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0] * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0] */ if (bootcs_found) { if (parx & (1 << 25)) { parx &= (1 << 14) - 1; /* Mask [13:0] */ flashbase = parx << 16; } else { parx &= (1 << 18) - 1; /* Mask [17:0] */ flashbase = parx << 12; } } else { - printf("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n"); + msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n"); } /* 4. Clean up */ physunmap(mmcr, getpagesize()); return 0; } /* Please keep this list alphabetically sorted by vendor/device. */ const struct penable chipset_enables[] = { {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530}, @@ -1426,29 +1426,29 @@ int chipset_flash_enable(void) struct pci_dev *dev = 0; int ret = -2; /* Nothing! */ int i; /* Now let's try to find the chipset we have... */ for (i = 0; chipset_enables[i].vendor_name != NULL; i++) { dev = pci_dev_find(chipset_enables[i].vendor_id, chipset_enables[i].device_id); if (dev) break; } if (dev) { - printf("Found chipset \"%s %s\", enabling flash write... ", + msg_pinfo("Found chipset \"%s %s\", enabling flash write... ", chipset_enables[i].vendor_name, chipset_enables[i].device_name); ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name); if (ret) - printf("FAILED!\n"); + msg_pinfo("FAILED!\n"); else - printf("OK.\n"); + msg_pinfo("OK.\n"); } - printf("This chipset supports the following protocols: %s.\n", + msg_pinfo("This chipset supports the following protocols: %s.\n", flashbuses_to_text(buses_supported)); return ret; } diff --git a/dmi.c b/dmi.c index d9f307f..a907a18 100644 --- a/dmi.c +++ b/dmi.c @@ -43,99 +43,99 @@ char *dmistrings[ARRAY_SIZE(dmidecode_names)]; #define DMI_MAX_ANSWER_LEN 4096 static char *get_dmi_string(const char *string_name) { FILE *dmidecode_pipe; char *result; char answerbuf[DMI_MAX_ANSWER_LEN]; char commandline[DMI_COMMAND_LEN_MAX + 40]; snprintf(commandline, sizeof(commandline), "%s -s %s", dmidecode_command, string_name); dmidecode_pipe = popen(commandline, "r"); if (!dmidecode_pipe) { - printf_debug("DMI pipe open error\n"); + msg_pdbg("DMI pipe open error\n"); return NULL; } if (!fgets(answerbuf, DMI_MAX_ANSWER_LEN, dmidecode_pipe)) { if(ferror(dmidecode_pipe)) { - printf_debug("DMI pipe read error\n"); + msg_pdbg("DMI pipe read error\n"); pclose(dmidecode_pipe); return NULL; } else { answerbuf[0] = 0; /* Hit EOF */ } } /* Toss all output above DMI_MAX_ANSWER_LEN away to prevent deadlock on pclose. */ while (!feof(dmidecode_pipe)) getc(dmidecode_pipe); if (pclose(dmidecode_pipe) != 0) { - printf_debug("DMI pipe close error\n"); + msg_pdbg("DMI pipe close error\n"); return NULL; } /* Chomp trailing newline. */ if (answerbuf[0] != 0 && answerbuf[strlen(answerbuf) - 1] == '\n') answerbuf[strlen(answerbuf) - 1] = 0; - printf_debug("DMI string %s: \"%s\"\n", string_name, answerbuf); + msg_pdbg("DMI string %s: \"%s\"\n", string_name, answerbuf); result = strdup(answerbuf); if (!result) puts("WARNING: Out of memory - DMI support fails"); return result; } void dmi_init(void) { int i; char *chassis_type; has_dmi_support = 1; for (i = 0; i < ARRAY_SIZE(dmidecode_names); i++) { dmistrings[i] = get_dmi_string(dmidecode_names[i]); if (!dmistrings[i]) { has_dmi_support = 0; return; } } chassis_type = get_dmi_string("chassis-type"); if (chassis_type && !strcmp(chassis_type, "Notebook")) { - printf_debug("Laptop detected via DMI\n"); + msg_pdbg("Laptop detected via DMI\n"); is_laptop = 1; } free(chassis_type); } /** * Does an substring/prefix/postfix/whole-string match. * * The pattern is matched as-is. The only metacharacters supported are '^' * at the beginning and '$' at the end. So you can look for "^prefix", * "suffix$", "substring" or "^complete string$". * * @param value The string to check. * @param pattern The pattern. * @return Nonzero if pattern matches. */ static int dmi_compare(const char *value, const char *pattern) { int anchored = 0; int patternlen; - printf_debug("matching %s against %s\n", value, pattern); + msg_pdbg("matching %s against %s\n", value, pattern); /* The empty string is part of all strings! */ if (pattern[0] == 0) return 1; if (pattern[0] == '^') { anchored = 1; pattern++; } patternlen = strlen(pattern); if (pattern[patternlen - 1] == '$') { int valuelen = strlen(value); patternlen--; diff --git a/hwaccess.c b/hwaccess.c index 10e67bd..0e889bb 100644 --- a/hwaccess.c +++ b/hwaccess.c @@ -31,27 +31,27 @@ int io_fd; #endif void get_io_perms(void) { #if defined (__sun) && (defined(__i386) || defined(__amd64)) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { #elif defined(__FreeBSD__) || defined (__DragonFly__) if ((io_fd = open("/dev/io", O_RDWR)) < 0) { #elif __DJGPP__ if (0) { #else if (iopl(3) != 0) { #endif - fprintf(stderr, "ERROR: Could not get I/O privileges (%s).\n" + msg_perr("ERROR: Could not get I/O privileges (%s).\n" "You need to be root.\n", strerror(errno)); exit(1); } } void release_io_perms(void) { #if defined(__FreeBSD__) || defined(__DragonFly__) close(io_fd); #endif } #ifdef __DJGPP__ diff --git a/ichspi.c b/ichspi.c index 35b9dbd..587fbcb 100644 --- a/ichspi.c +++ b/ichspi.c @@ -28,37 +28,26 @@ * ST M25P80 * ST M25P16 * ST M25P32 already tested * ST M25P64 * AT 25DF321 already tested * */ #include <string.h> #include "flash.h" #include "chipdrivers.h" #include "spi.h" -/* Change this to #define if you want lowlevel debugging of commands - * sent to the ICH/VIA SPI controller. - */ -#undef COMM_DEBUG - -#ifdef COMM_DEBUG -#define msg_comm_debug printf_debug -#else -#define msg_comm_debug(...) do {} while (0) -#endif - /* ICH9 controller register definition */ #define ICH9_REG_FADDR 0x08 /* 32 Bits */ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ #define ICH9_REG_SSFS 0x90 /* 08 Bits */ #define SSFS_SCIP 0x00000001 #define SSFS_CDS 0x00000004 #define SSFS_FCERR 0x00000008 #define SSFS_AEL 0x00000010 #define ICH9_REG_SSFC 0x91 /* 24 Bits */ #define SSFC_SCGO 0x00000200 #define SSFC_ACS 0x00000400 @@ -227,46 +216,46 @@ static int find_preop(OPCODES *op, uint8_t preop) } return -1; } /* Create a struct OPCODES based on what we find in the locked down chipset. */ static int generate_opcodes(OPCODES * op) { int a; uint16_t preop, optype; uint32_t opmenu[2]; if (op == NULL) { - printf_debug("\n%s: null OPCODES pointer!\n", __func__); + msg_pdbg("\n%s: null OPCODES pointer!\n", __func__); return -1; } switch (spi_controller) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: preop = REGREAD16(ICH7_REG_PREOP); optype = REGREAD16(ICH7_REG_OPTYPE); opmenu[0] = REGREAD32(ICH7_REG_OPMENU); opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4); break; case SPI_CONTROLLER_ICH9: preop = REGREAD16(ICH9_REG_PREOP); optype = REGREAD16(ICH9_REG_OPTYPE); opmenu[0] = REGREAD32(ICH9_REG_OPMENU); opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4); break; default: - printf_debug("%s: unsupported chipset\n", __func__); + msg_pdbg("%s: unsupported chipset\n", __func__); return -1; } op->preop[0] = (uint8_t) preop; op->preop[1] = (uint8_t) (preop >> 8); for (a = 0; a < 8; a++) { op->opcode[a].spi_type = (uint8_t) (optype & 0x3); optype >>= 2; } for (a = 0; a < 4; a++) { op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff); @@ -305,79 +294,79 @@ int program_opcodes(OPCODES * op) /* Program Allowable Opcodes 0 - 3 */ opmenu[0] = 0; for (a = 0; a < 4; a++) { opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8); } /*Program Allowable Opcodes 4 - 7 */ opmenu[1] = 0; for (a = 4; a < 8; a++) { opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8); } - printf_debug("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); + msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); switch (spi_controller) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: REGWRITE16(ICH7_REG_PREOP, preop); REGWRITE16(ICH7_REG_OPTYPE, optype); REGWRITE32(ICH7_REG_OPMENU, opmenu[0]); REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]); break; case SPI_CONTROLLER_ICH9: REGWRITE16(ICH9_REG_PREOP, preop); REGWRITE16(ICH9_REG_OPTYPE, optype); REGWRITE32(ICH9_REG_OPMENU, opmenu[0]); REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]); break; default: - printf_debug("%s: unsupported chipset\n", __func__); + msg_pdbg("%s: unsupported chipset\n", __func__); return -1; } return 0; } /* This function generates OPCODES from or programs OPCODES to ICH according to * the chipset's SPI configuration lock. * * It should be called before ICH sends any spi command. */ int ich_init_opcodes(void) { int rc = 0; OPCODES *curopcodes_done; if (curopcodes) return 0; if (ichspi_lock) { - printf_debug("Generating OPCODES... "); + msg_pdbg("Generating OPCODES... "); curopcodes_done = &O_EXISTING; rc = generate_opcodes(curopcodes_done); } else { - printf_debug("Programming OPCODES... "); + msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; rc = program_opcodes(curopcodes_done); } if (rc) { curopcodes = NULL; - printf_debug("failed\n"); + msg_pdbg("failed\n"); return 1; } else { curopcodes = curopcodes_done; - printf_debug("done\n"); + msg_pdbg("done\n"); return 0; } } static int ich7_run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data, int maxdata) { int write_cmd = 0; int timeout; uint32_t temp32 = 0; uint16_t temp16; uint32_t a; uint64_t opmenu; @@ -429,27 +418,27 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, } /* Select opcode */ opmenu = REGREAD32(ICH7_REG_OPMENU); opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32; for (opcode_index = 0; opcode_index < 8; opcode_index++) { if ((opmenu & 0xff) == op.opcode) { break; } opmenu >>= 8; } if (opcode_index == 8) { - printf_debug("Opcode %x not found.\n", op.opcode); + msg_pdbg("Opcode %x not found.\n", op.opcode); return 1; } temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4; /* Handle Atomic */ switch (op.atomic) { case 2: /* Select second preop. */ temp16 |= SPIC_SPOP; /* And fall through. */ case 1: /* Atomic command (preop+op) */ temp16 |= SPIC_ACS; @@ -458,31 +447,31 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, /* Start */ temp16 |= SPIC_SCGO; /* write it */ REGWRITE16(ICH7_REG_SPIC, temp16); /* wait for cycle complete */ timeout = 100 * 1000 * 60; // 60s is a looong timeout. while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) { programmer_delay(10); } if (!timeout) { - printf_debug("timeout\n"); + msg_pdbg("timeout\n"); } if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) { - printf_debug("Transaction error!\n"); + msg_pdbg("Transaction error!\n"); return 1; } if ((!write_cmd) && (datalength != 0)) { for (a = 0; a < datalength; a++) { if ((a % 4) == 0) { temp32 = REGREAD32(ICH7_REG_SPID0 + (a)); } data[a] = (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) >> ((a % 4) * 8); } @@ -547,27 +536,27 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, } /* Select opcode */ opmenu = REGREAD32(ICH9_REG_OPMENU); opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32; for (opcode_index = 0; opcode_index < 8; opcode_index++) { if ((opmenu & 0xff) == op.opcode) { break; } opmenu >>= 8; } if (opcode_index == 8) { - printf_debug("Opcode %x not found.\n", op.opcode); + msg_pdbg("Opcode %x not found.\n", op.opcode); return 1; } temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4); /* Handle Atomic */ switch (op.atomic) { case 2: /* Select second preop. */ temp32 |= SSFC_SPOP; /* And fall through. */ case 1: /* Atomic command (preop+op) */ temp32 |= SSFC_ACS; @@ -576,100 +565,100 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, /* Start */ temp32 |= SSFC_SCGO; /* write it */ REGWRITE32(ICH9_REG_SSFS, temp32); /*wait for cycle complete */ timeout = 100 * 1000 * 60; // 60s is a looong timeout. while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) { programmer_delay(10); } if (!timeout) { - printf_debug("timeout\n"); + msg_pdbg("timeout\n"); } if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) { - printf_debug("Transaction error!\n"); + msg_pdbg("Transaction error!\n"); return 1; } if ((!write_cmd) && (datalength != 0)) { for (a = 0; a < datalength; a++) { if ((a % 4) == 0) { temp32 = REGREAD32(ICH9_REG_FDATA0 + (a)); } data[a] = (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) >> ((a % 4) * 8); } } return 0; } static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data) { switch (spi_controller) { case SPI_CONTROLLER_VIA: if (datalength > 16) { - fprintf(stderr, "%s: Internal command size error for " + msg_pdbg("%s: Internal command size error for " "opcode 0x%02x, got datalength=%i, want <=16\n", __func__, op.opcode, datalength); return SPI_INVALID_LENGTH; } return ich7_run_opcode(op, offset, datalength, data, 16); case SPI_CONTROLLER_ICH7: if (datalength > 64) { - fprintf(stderr, "%s: Internal command size error for " + msg_pdbg("%s: Internal command size error for " "opcode 0x%02x, got datalength=%i, want <=16\n", __func__, op.opcode, datalength); return SPI_INVALID_LENGTH; } return ich7_run_opcode(op, offset, datalength, data, 64); case SPI_CONTROLLER_ICH9: if (datalength > 64) { - fprintf(stderr, "%s: Internal command size error for " + msg_pdbg("%s: Internal command size error for " "opcode 0x%02x, got datalength=%i, want <=16\n", __func__, op.opcode, datalength); return SPI_INVALID_LENGTH; } return ich9_run_opcode(op, offset, datalength, data); default: - printf_debug("%s: unsupported chipset\n", __func__); + msg_pdbg("%s: unsupported chipset\n", __func__); } /* If we ever get here, something really weird happened */ return -1; } static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, int offset, int maxdata) { int page_size = flash->page_size; uint32_t remaining = page_size; int towrite; - msg_comm_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n", + msg_pspew("ich_spi_write_page: offset=%d, number=%d, buf=%p\n", offset, page_size, bytes); for (; remaining > 0; remaining -= towrite) { towrite = min(remaining, maxdata); if (spi_nbyte_program(offset + (page_size - remaining), &bytes[page_size - remaining], towrite)) { - printf_debug("Error writing"); + msg_pdbg("Error writing"); return 1; } } return 0; } int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) { int maxdata = 64; if (spi_controller == SPI_CONTROLLER_VIA) maxdata = 16; @@ -677,169 +666,169 @@ int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) return spi_read_chunked(flash, buf, start, len, maxdata); } int ich_spi_write_256(struct flashchip *flash, uint8_t * buf) { int i, j, rc = 0; int total_size = flash->total_size * 1024; int page_size = flash->page_size; int erase_size = 64 * 1024; int maxdata = 64; spi_disable_blockprotect(); /* Erase first */ - printf("Erasing flash before programming... "); + msg_pinfo("Erasing flash before programming... "); if (erase_flash(flash)) { - fprintf(stderr, "ERASE FAILED!\n"); + msg_perr("ERASE FAILED!\n"); return -1; } - printf("done.\n"); + msg_pinfo("done.\n"); - printf("Programming page: \n"); + msg_pinfo("Programming page: \n"); for (i = 0; i < total_size / erase_size; i++) { if (spi_controller == SPI_CONTROLLER_VIA) maxdata = 16; for (j = 0; j < erase_size / page_size; j++) { ich_spi_write_page(flash, (void *)(buf + (i * erase_size) + (j * page_size)), (i * erase_size) + (j * page_size), maxdata); } } - printf("\n"); + msg_pinfo("\n"); return rc; } int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int result; int opcode_index = -1; const unsigned char cmd = *writearr; OPCODE *opcode; uint32_t addr = 0; uint8_t *data; int count; /* find cmd in opcodes-table */ opcode_index = find_opcode(curopcodes, cmd); if (opcode_index == -1) { /* FIXME: Reprogram opcodes if possible. Autodetect type of * opcode by checking readcnt/writecnt. */ - printf_debug("Invalid OPCODE 0x%02x\n", cmd); + msg_pdbg("Invalid OPCODE 0x%02x\n", cmd); return SPI_INVALID_OPCODE; } opcode = &(curopcodes->opcode[opcode_index]); /* The following valid writecnt/readcnt combinations exist: * writecnt = 4, readcnt >= 0 * writecnt = 1, readcnt >= 0 * writecnt >= 4, readcnt = 0 * writecnt >= 1, readcnt = 0 * writecnt >= 1 is guaranteed for all commands. */ if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) && (writecnt != 4)) { - fprintf(stderr, "%s: Internal command size error for opcode " + msg_pdbg("%s: Internal command size error for opcode " "0x%02x, got writecnt=%i, want =4\n", __func__, cmd, writecnt); return SPI_INVALID_LENGTH; } if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) && (writecnt != 1)) { - fprintf(stderr, "%s: Internal command size error for opcode " + msg_pdbg("%s: Internal command size error for opcode " "0x%02x, got writecnt=%i, want =1\n", __func__, cmd, writecnt); return SPI_INVALID_LENGTH; } if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) && (writecnt < 4)) { - fprintf(stderr, "%s: Internal command size error for opcode " + msg_pdbg("%s: Internal command size error for opcode " "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd, writecnt); return SPI_INVALID_LENGTH; } if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) && (readcnt)) { - fprintf(stderr, "%s: Internal command size error for opcode " + msg_pdbg("%s: Internal command size error for opcode " "0x%02x, got readcnt=%i, want =0\n", __func__, cmd, readcnt); return SPI_INVALID_LENGTH; } /* if opcode-type requires an address */ if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS || opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); } /* translate read/write array/count */ if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) { data = (uint8_t *) (writearr + 1); count = writecnt - 1; } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { data = (uint8_t *) (writearr + 4); count = writecnt - 4; } else { data = (uint8_t *) readarr; count = readcnt; } result = run_opcode(*opcode, addr, count, data); if (result) { - printf_debug("run OPCODE 0x%02x failed\n", opcode->opcode); + msg_pdbg("run OPCODE 0x%02x failed\n", opcode->opcode); } return result; } int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; int i; int oppos, preoppos; for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) { if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) { /* Next command is valid. */ preoppos = find_preop(curopcodes, cmds->writearr[0]); oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]); if ((oppos == -1) && (preoppos != -1)) { /* Current command is listed as preopcode in * ICH struct OPCODES, but next command is not * listed as opcode in that struct. * Check for command sanity, then * try to reprogram the ICH opcode list. */ if (find_preop(curopcodes, (cmds + 1)->writearr[0]) != -1) { - fprintf(stderr, "%s: Two subsequent " + msg_pdbg("%s: Two subsequent " "preopcodes 0x%02x and 0x%02x, " "ignoring the first.\n", __func__, cmds->writearr[0], (cmds + 1)->writearr[0]); continue; } /* If the chipset is locked down, we'll fail * during execution of the next command anyway. * No need to bother with fixups. */ if (!ichspi_lock) { - printf_debug("%s: FIXME: Add on-the-fly" + msg_pdbg("%s: FIXME: Add on-the-fly" " reprogramming of the " "chipset opcode list.\n", __func__); /* FIXME: Reprogram opcode menu. * Find a less-useful opcode, replace it * with the wanted opcode, detect optype * and reprogram the opcode menu. * Update oppos so the next if-statement * can do something useful. */ //curopcodes.opcode[lessusefulindex] = (cmds + 1)->writearr[0]); //update_optypes(curopcodes); //program_opcodes(curopcodes); diff --git a/internal.c b/internal.c index 39edd10..672b41f 100644 --- a/internal.c +++ b/internal.c @@ -146,40 +146,40 @@ int internal_init(void) pci_scan_bus(pacc); /* We want to get the list of devices */ /* We look at the lbtable first to see if we need a * mainboard specific flash enable sequence. */ coreboot_init(); dmi_init(); /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); /* Warn if a laptop is detected. */ if (is_laptop) - printf("========================================================================\n" + msg_pinfo("========================================================================\n" "WARNING! You seem to be running flashrom on a laptop.\n" "Laptops, notebooks and netbooks are difficult to support and we recommend\n" "to use the vendor flashing utility. The embedded controller (EC) in these\n" "machines often interacts badly with flashing.\n" "See http://www.flashrom.org/Laptops for details.\n" "========================================================================\n"); /* try to enable it. Failure IS an option, since not all motherboards * really need this to be done, etc., etc. */ ret = chipset_flash_enable(); if (ret == -2) { - printf("WARNING: No chipset found. Flash detection " + msg_pinfo("WARNING: No chipset found. Flash detection " "will most likely fail.\n"); } /* Probe for IT87* LPC->SPI translation unconditionally. */ it87xx_probe_spi_flash(NULL); board_flash_enable(lb_vendor, lb_part); /* Even if chipset init returns an error code, we don't want to abort. * The error code might have been a warning only. * Besides that, we don't check the board enable return code either. */ return 0; diff --git a/pcidev.c b/pcidev.c index 818819a..add1fce 100644 --- a/pcidev.c +++ b/pcidev.c @@ -35,48 +35,48 @@ uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, /* FIXME: 64 bit memory BARs need a 64 bit addr. */ uint32_t addr; for (i = 0; devs[i].device_name != NULL; i++) { if (dev->device_id != devs[i].device_id) continue; /* * Don't use dev->base_addr[x] (as value for 'bar'), won't * work on older libpci. */ addr = pci_read_long(dev, bar); - printf("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", + msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", devs[i].vendor_name, devs[i].device_name, dev->vendor_id, dev->device_id, dev->bus, dev->dev, dev->func); msg_pdbg("Requested BAR is %s", (addr & 0x1) ? "IO" : "MEM"); if (addr & 0x1) { /* Mask off IO space indicator and reserved bit. */ msg_pdbg("\n"); addr &= ~0x3; } else { msg_pdbg(", %sbit, %sprefetchable\n", ((addr & 0x6) == 0x0) ? "32" : (((addr & 0x6) == 0x4) ? "64" : "reserved"), (addr & 0x8) ? "" : "not "); /* Mask off Mem space indicator, 32/64bit type indicator * and Prefetchable indicator. */ addr &= ~0xf; } if (devs[i].status == NT) { - printf("===\nThis PCI device is UNTESTED. Please " + msg_pinfo("===\nThis PCI device is UNTESTED. Please " "report the 'flashrom -p xxxx' output \n" "to flashrom(a)flashrom.org if it works " "for you. Thank you for your help!\n===\n"); } return addr; } return 0; } uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, struct pcidev_status *devs, char *pcidev_bdf) @@ -85,54 +85,54 @@ uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, char *msg = NULL; int found = 0; uint32_t addr = 0, curaddr = 0; pacc = pci_alloc(); /* Get the pci_access structure */ pci_init(pacc); /* Initialize the PCI library */ pci_scan_bus(pacc); /* We want to get the list of devices */ pci_filter_init(pacc, &filter); /* Filter by vendor and also bb:dd.f (if supplied by the user). */ filter.vendor = vendor_id; if (pcidev_bdf != NULL) { if ((msg = pci_filter_parse_slot(&filter, pcidev_bdf))) { - fprintf(stderr, "Error: %s\n", msg); + msg_perr("Error: %s\n", msg); exit(1); } } for (dev = pacc->devices; dev; dev = dev->next) { if (pci_filter_match(&filter, dev)) { if ((addr = pcidev_validate(dev, bar, devs)) != 0) { curaddr = addr; pcidev_dev = dev; found++; } } } /* Only continue if exactly one supported PCI dev has been found. */ if (found == 0) { - fprintf(stderr, "Error: No supported PCI device found.\n"); + msg_perr("Error: No supported PCI device found.\n"); exit(1); } else if (found > 1) { - fprintf(stderr, "Error: Multiple supported PCI devices found. " + msg_perr("Error: Multiple supported PCI devices found. " "Use 'flashrom -p xxxx:bb:dd.f' \n" "to explicitly select the card with the given BDF " "(PCI bus, device, function).\n"); exit(1); } return curaddr; } void print_supported_pcidevs(struct pcidev_status *devs) { int i; for (i = 0; devs[i].vendor_name != NULL; i++) { - printf("%s %s [%02x:%02x]%s\n", devs[i].vendor_name, + msg_pinfo("%s %s [%02x:%02x]%s\n", devs[i].vendor_name, devs[i].device_name, devs[i].vendor_id, devs[i].device_id, (devs[i].status == NT) ? " (untested)" : ""); } } diff --git a/physmap.c b/physmap.c index 38a395c..efd641c 100644 --- a/physmap.c +++ b/physmap.c @@ -160,76 +160,76 @@ void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) perror("Critical error: open(" MEM_DEV ")"); exit(2); } } virt_addr = mmap(0, len, PROT_READ, MAP_SHARED, fd_mem_cached, (off_t)phys_addr); return MAP_FAILED == virt_addr ? NULL : virt_addr; } void physunmap(void *virt_addr, size_t len) { if (len == 0) { - printf_debug("Not unmapping zero size at %p\n", virt_addr); + msg_pdbg("Not unmapping zero size at %p\n", virt_addr); return; } munmap(virt_addr, len); } #endif #define PHYSMAP_NOFAIL 0 #define PHYSMAP_MAYFAIL 1 #define PHYSMAP_RW 0 #define PHYSMAP_RO 1 void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, int mayfail, int readonly) { void *virt_addr; if (len == 0) { - printf_debug("Not mapping %s, zero size at 0x%08lx.\n", + msg_pdbg("Not mapping %s, zero size at 0x%08lx.\n", descr, phys_addr); return NULL; } if ((getpagesize() - 1) & len) { - fprintf(stderr, "Mapping %s at 0x%08lx, unaligned size 0x%lx.\n", + msg_perr("Mapping %s at 0x%08lx, unaligned size 0x%lx.\n", descr, phys_addr, (unsigned long)len); } if ((getpagesize() - 1) & phys_addr) { - fprintf(stderr, "Mapping %s, 0x%lx bytes at unaligned 0x%08lx.\n", + msg_perr("Mapping %s, 0x%lx bytes at unaligned 0x%08lx.\n", descr, (unsigned long)len, phys_addr); } if (readonly) { virt_addr = sys_physmap_ro_cached(phys_addr, len); } else { virt_addr = sys_physmap_rw_uncached(phys_addr, len); } if (NULL == virt_addr) { if (NULL == descr) descr = "memory"; - fprintf(stderr, "Error accessing %s, 0x%lx bytes at 0x%08lx\n", descr, (unsigned long)len, phys_addr); + msg_perr("Error accessing %s, 0x%lx bytes at 0x%08lx\n", descr, (unsigned long)len, phys_addr); perror(MEM_DEV " mmap failed"); if (EINVAL == errno) { - fprintf(stderr, "In Linux this error can be caused by the CONFIG_NONPROMISC_DEVMEM (<2.6.27),\n"); - fprintf(stderr, "CONFIG_STRICT_DEVMEM (>=2.6.27) and CONFIG_X86_PAT kernel options.\n"); - fprintf(stderr, "Please check if either is enabled in your kernel before reporting a failure.\n"); - fprintf(stderr, "You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); - fprintf(stderr, "disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); + msg_perr("In Linux this error can be caused by the CONFIG_NONPROMISC_DEVMEM (<2.6.27),\n"); + msg_perr("CONFIG_STRICT_DEVMEM (>=2.6.27) and CONFIG_X86_PAT kernel options.\n"); + msg_perr("Please check if either is enabled in your kernel before reporting a failure.\n"); + msg_perr("You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); + msg_perr("disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); } if (!mayfail) exit(3); } return virt_addr; } void *physmap(const char *descr, unsigned long phys_addr, size_t len) { return physmap_common(descr, phys_addr, len, PHYSMAP_NOFAIL, PHYSMAP_RW); } @@ -295,45 +295,45 @@ int wrmsr(int addr, msr_t msr) if (errno == EIO) return -1; return 0; } int setup_cpu_msr(int cpu) { char msrfilename[64]; memset(msrfilename, 0, 64); sprintf(msrfilename, "/dev/cpu/%d/msr", cpu); if (fd_msr != -1) { - printf("MSR was already initialized\n"); + msg_pinfo("MSR was already initialized\n"); return -1; } fd_msr = open(msrfilename, O_RDWR); if (fd_msr < 0) { perror("Error while opening /dev/cpu/0/msr"); - printf("Did you run 'modprobe msr'?\n"); + msg_pinfo("Did you run 'modprobe msr'?\n"); return -1; } return 0; } void cleanup_cpu_msr(void) { if (fd_msr == -1) { - printf("No MSR initialized.\n"); + msg_pinfo("No MSR initialized.\n"); return; } close(fd_msr); /* Clear MSR file descriptor */ fd_msr = -1; } #else #if defined(__FreeBSD__) || defined(__DragonFly__) #include <sys/ioctl.h> typedef struct { @@ -378,45 +378,45 @@ int wrmsr(int addr, msr_t msr) exit(1); } return 0; } int setup_cpu_msr(int cpu) { char msrfilename[64]; memset(msrfilename, 0, 64); sprintf(msrfilename, "/dev/cpu%d", cpu); if (fd_msr != -1) { - printf("MSR was already initialized\n"); + msg_pinfo("MSR was already initialized\n"); return -1; } fd_msr = open(msrfilename, O_RDWR); if (fd_msr < 0) { perror("Error while opening /dev/cpu0"); - printf("Did you install ports/sysutils/devcpu?\n"); + msg_pinfo("Did you install ports/sysutils/devcpu?\n"); return -1; } return 0; } void cleanup_cpu_msr(void) { if (fd_msr == -1) { - printf("No MSR initialized.\n"); + msg_pinfo("No MSR initialized.\n"); return; } close(fd_msr); /* Clear MSR file descriptor */ fd_msr = -1; } #else #ifdef __DARWIN__ int setup_cpu_msr(int cpu) @@ -434,25 +434,25 @@ msr_t rdmsr(int addr) { msr_t ret = { 0xffffffff, 0xffffffff }; return ret; } int wrmsr(int addr, msr_t msr) { return -1; } int setup_cpu_msr(int cpu) { - printf("No MSR support for your OS yet.\n"); + msg_pinfo("No MSR support for your OS yet.\n"); return -1; } void cleanup_cpu_msr(void) { // Nothing, yet. } #endif #endif #endif diff --git a/spi.c b/spi.c index 8bbbe6e..9bb4687 100644 --- a/spi.c +++ b/spi.c @@ -120,39 +120,39 @@ const struct spi_programmer spi_programmer[] = { .write_256 = spi_chip_write_1, }, #endif {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ }; const int spi_programmer_count = ARRAY_SIZE(spi_programmer); int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { if (!spi_programmer[spi_controller].command) { - fprintf(stderr, "%s called, but SPI is unsupported on this " + msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug.\n", __func__); return 1; } return spi_programmer[spi_controller].command(writecnt, readcnt, writearr, readarr); } int spi_send_multicommand(struct spi_command *cmds) { if (!spi_programmer[spi_controller].multicommand) { - fprintf(stderr, "%s called, but SPI is unsupported on this " + msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug.\n", __func__); return 1; } return spi_programmer[spi_controller].multicommand(cmds); } int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { struct spi_command cmd[] = { { .writecnt = writecnt, @@ -172,41 +172,41 @@ int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, int default_spi_send_multicommand(struct spi_command *cmds) { int result = 0; for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) { result = spi_send_command(cmds->writecnt, cmds->readcnt, cmds->writearr, cmds->readarr); } return result; } int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { if (!spi_programmer[spi_controller].read) { - fprintf(stderr, "%s called, but SPI read is unsupported on this" + msg_perr("%s called, but SPI read is unsupported on this" " hardware. Please report a bug.\n", __func__); return 1; } return spi_programmer[spi_controller].read(flash, buf, start, len); } /* * Program chip using page (256 bytes) programming. * Some SPI masters can't do this, they use single byte programming instead. */ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) { if (!spi_programmer[spi_controller].write_256) { - fprintf(stderr, "%s called, but SPI page write is unsupported " + msg_perr("%s called, but SPI page write is unsupported " " on this hardware. Please report a bug.\n", __func__); return 1; } return spi_programmer[spi_controller].write_256(flash, buf); } uint32_t spi_get_valid_read_addr(void) { /* Need to return BBAR for ICH chipsets. */ return 0; } -- 1.6.6

3 7

[commit] r997 - trunk
by repository service 07 May '10

07 May '10

Author: snelson Date: Fri May 7 22:09:04 2010 New Revision: 997 URL: http://flashrom.org/trac/coreboot/changeset/997 Log: convert programmer print messages to msg_p* convert general print messages to msg_g* a few fixes as suggested by Carl-Daniel Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/cbtable.c trunk/chipset_enable.c trunk/dmi.c trunk/flashrom.c trunk/hwaccess.c trunk/ichspi.c trunk/pcidev.c trunk/physmap.c trunk/spi.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/board_enable.c Fri May 7 22:09:04 2010 (r997) @@ -87,7 +87,7 @@ ret = 0; break; default: - printf_debug("Unhandled Super I/O type!\n"); + msg_pdbg("Unhandled Super I/O type!\n"); ret = -1; break; } @@ -108,7 +108,7 @@ /* Is this the W83627HF? */ if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */ - fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n", + msg_perr("\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n", name, sio_read(port, 0x20)); w836xx_ext_leave(port); return -1; @@ -148,7 +148,7 @@ /* Is this the W83627THF? */ if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */ - fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n", + msg_perr("\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n", name, sio_read(port, 0x20)); w836xx_ext_leave(port); return -1; @@ -253,20 +253,20 @@ uint8_t id, val; if (gpio_bank > 4) { - fprintf(stderr, "PC87360: Invalid GPIO %d\n", gpio); + msg_perr("PC87360: Invalid GPIO %d\n", gpio); return -1; } id = sio_read(0x2E, 0x20); if (id != 0xE1) { - fprintf(stderr, "PC87360: unexpected ID %02x\n", id); + msg_perr("PC87360: unexpected ID %02x\n", id); return -1; } sio_write(0x2E, 0x07, 0x07); /* Select GPIO device */ baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) { - fprintf (stderr, "PC87360: invalid GPIO base address %04x\n", + msg_perr("PC87360: invalid GPIO base address %04x\n", baseport); return -1; } @@ -300,7 +300,7 @@ case 0x3337: /* VT8237A */ break; default: - fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); + msg_perr("\nERROR: VT823x ISA bridge not found.\n"); return -1; } @@ -319,7 +319,7 @@ val |= 0x01; pci_write_byte(dev, 0xE4, val); } else { - fprintf(stderr, "\nERROR: " + msg_perr("\nERROR: " "VT823x GPIO%02d is not implemented.\n", gpio); return -1; } @@ -411,7 +411,7 @@ } if (i == ASUSP5A_LOOP) { - printf("%s: Unable to contact device.\n", name); + msg_perr("%s: Unable to contact device.\n", name); return -1; } @@ -427,7 +427,7 @@ } if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) { - printf("%s: failed to read device.\n", name); + msg_perr("%s: failed to read device.\n", name); return -1; } @@ -454,7 +454,7 @@ } if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) { - printf("%s: failed to write to device.\n", name); + msg_perr("%s: failed to write to device.\n", name); return -1; } @@ -492,8 +492,7 @@ dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */ if (!dev) { - fprintf(stderr, - "\nERROR: NVIDIA nForce4 ISA bridge not found.\n"); + msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n"); return -1; } @@ -513,7 +512,7 @@ uint8_t tmp; if ((gpio < 0) || (gpio >= 0x40)) { - fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio); + msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio); return -1; } @@ -531,8 +530,7 @@ case 0x0264: /* MCP51 */ break; default: - fprintf(stderr, - "\nERROR: no NVIDIA LPC/SMBus controller found.\n"); + msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n"); return -1; } break; @@ -661,20 +659,20 @@ dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */ if (!dev) { - fprintf(stderr, "\nERROR: Intel PIIX4 ISA bridge not found.\n"); + msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n"); return -1; } /* sanity check */ if (gpo > 30) { - fprintf(stderr, "\nERROR: Intel PIIX4 has no GPO%d.\n", gpo); + msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo); return -1; } /* these are dual function pins which are most likely in use already */ if (((gpo >= 1) && (gpo <= 7)) || ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) { - fprintf(stderr, "\nERROR: Unsupported PIIX4 GPO%d.\n", gpo); + msg_perr("\nERROR: Unsupported PIIX4 GPO%d.\n", gpo); return -1; } @@ -703,7 +701,7 @@ dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */ if (!dev) { - fprintf(stderr, "\nERROR: Intel PIIX4 PM not found.\n"); + msg_perr("\nERROR: Intel PIIX4 PM not found.\n"); return -1; } @@ -805,7 +803,7 @@ } if (!dev) { - fprintf(stderr, "\nERROR: No Known Intel LPC Bridge found.\n"); + msg_perr("\nERROR: No Known Intel LPC Bridge found.\n"); return -1; } @@ -823,12 +821,12 @@ allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01; if (!allowed) { - fprintf(stderr, "\nERROR: This Intel LPC Bridge does not allow" + msg_perr("\nERROR: This Intel LPC Bridge does not allow" " setting GPIO%02d\n", gpio); return -1; } - printf("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n", + msg_pdbg("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n", raise ? "Rais" : "Dropp", gpio); if (gpio < 32) { @@ -847,7 +845,7 @@ if (dev->device_id > 0x2800) { tmp = INL(base); if (!(tmp & (1 << gpio))) { - fprintf(stderr, "\nERROR: This Intel LPC Bridge" + msg_perr("\nERROR: This Intel LPC Bridge" " does not allow setting GPIO%02d\n", gpio); return -1; @@ -879,7 +877,7 @@ if (dev->device_id > 0x2800) { tmp = INL(base + 30); if (!(tmp & (1 << gpio))) { - fprintf(stderr, "\nERROR: This Intel LPC Bridge" + msg_perr("\nERROR: This Intel LPC Bridge" " does not allow setting GPIO%02d\n", gpio + 32); return -1; @@ -908,7 +906,7 @@ tmp = INL(base + 40); if (!(tmp & (1 << gpio))) { - fprintf(stderr, "\nERROR: This Intel LPC Bridge does " + msg_perr("\nERROR: This Intel LPC Bridge does " "not allow setting GPIO%02d\n", gpio + 64); return -1; } @@ -1051,11 +1049,11 @@ /* VT82C686 Power management */ dev = pci_dev_find(0x1106, 0x3057); if (!dev) { - fprintf(stderr, "\nERROR: VT82C686 PM device not found.\n"); + msg_perr("\nERROR: VT82C686 PM device not found.\n"); return -1; } - printf("\nVIA Apollo ACPI: %sing GPIO%02d.\n", + msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n", raise ? "Rais" : "Dropp", gpio); /* select GPO function on multiplexed pins */ @@ -1118,7 +1116,7 @@ dev = pci_dev_find(0x1039, 0x0962); if (!dev) { - fprintf(stderr, "Expected south bridge not found\n"); + msg_perr("Expected south bridge not found\n"); return 1; } @@ -1151,7 +1149,7 @@ /* Verify the chip ID. */ OUTB(0x55, sio_port); /* Enable configuration. */ if (sio_read(sio_port, 0x20) != chip_id) { - fprintf(stderr, "\nERROR: SMSC Super I/O not found.\n"); + msg_perr("\nERROR: SMSC Super I/O not found.\n"); goto out; } @@ -1163,7 +1161,7 @@ } if (rt_port == 0) { - fprintf(stderr, "\nERROR: " + msg_perr("\nERROR: " "Super I/O runtime interface not available.\n"); } out: @@ -1183,7 +1181,7 @@ dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */ if (!dev) { - fprintf(stderr, "\nERROR: Intel 82801AA ISA bridge not found.\n"); + msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n"); return -1; } @@ -1218,7 +1216,7 @@ w836xx_ext_leave(0x2E); if (id != 0x8701) { - fprintf(stderr, "\nERROR: IT8703F Super I/O not found.\n"); + msg_perr("\nERROR: IT8703F Super I/O not found.\n"); return -1; } @@ -1229,7 +1227,7 @@ w836xx_ext_leave(0x2E); if (!base) { - fprintf(stderr, "\nERROR: Failed to read IT8703F Super I/O GPIO" + msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO" " Base.\n"); return -1; } @@ -1259,8 +1257,7 @@ /* Check line */ if ((port > 4) || /* also catches unsigned -1 */ ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) { - fprintf(stderr, - "\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line); + msg_perr("\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line); return -1; } @@ -1270,7 +1267,7 @@ exit_conf_mode_ite(0x2E); if (id != 0x8712) { - fprintf(stderr, "\nERROR: IT8712F Super I/O not found.\n"); + msg_perr("\nERROR: IT8712F Super I/O not found.\n"); return -1; } @@ -1281,7 +1278,7 @@ exit_conf_mode_ite(0x2E); if (!base) { - fprintf(stderr, "\nERROR: Failed to read IT8712F Super I/O GPIO" + msg_perr("\nERROR: Failed to read IT8712F Super I/O GPIO" " Base.\n"); return -1; } @@ -1450,10 +1447,10 @@ if (partmatch) { /* a second entry has a matching part name */ - printf("AMBIGUOUS BOARD NAME: %s\n", part); - printf("At least vendors '%s' and '%s' match.\n", + msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part); + msg_pinfo("At least vendors '%s' and '%s' match.\n", partmatch->lb_vendor, board->lb_vendor); - printf("Please use the full -m vendor:part syntax.\n"); + msg_perr("Please use the full -m vendor:part syntax.\n"); return NULL; } partmatch = board; @@ -1467,7 +1464,7 @@ * coreboot table. If it was, the coreboot implementor is * expected to fix flashrom, too. */ - printf("\nUnknown vendor:board from -m option: %s:%s\n\n", + msg_perr("\nUnknown vendor:board from -m option: %s:%s\n\n", vendor, part); } return NULL; @@ -1507,7 +1504,7 @@ if (board->dmi_pattern) { if (!has_dmi_support) { - fprintf(stderr, "WARNING: Can't autodetect %s %s," + msg_perr("WARNING: Can't autodetect %s %s," " DMI info unavailable.\n", board->vendor_name, board->board_name); continue; @@ -1536,7 +1533,7 @@ if (board && board->status == NT) { if (!force_boardenable) { - printf("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" + msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" "code has not been tested, and thus will not not be executed by default.\n" "Depending on your hardware environment, erasing, writing or even probing\n" "can fail without running the board specific code.\n\n" @@ -1545,7 +1542,7 @@ board->vendor_name, board->board_name); board = NULL; } else { - printf("NOTE: Running an untested board enable procedure.\n" + msg_pinfo("NOTE: Running an untested board enable procedure.\n" "Please report success/failure to flashrom(a)flashrom.org.\n"); } } @@ -1556,15 +1553,15 @@ board->max_rom_decode_parallel * 1024; if (board->enable != NULL) { - printf("Disabling flash write protection for " + msg_pinfo("Disabling flash write protection for " "board \"%s %s\"... ", board->vendor_name, board->board_name); ret = board->enable(board->vendor_name); if (ret) - printf("FAILED!\n"); + msg_pinfo("FAILED!\n"); else - printf("OK.\n"); + msg_pinfo("OK.\n"); } } Modified: trunk/cbtable.c ============================================================================== --- trunk/cbtable.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/cbtable.c Fri May 7 22:09:04 2010 (r997) @@ -112,29 +112,29 @@ (struct lb_record *)(((char *)base) + addr + sizeof(*head)); if (memcmp(head->signature, "LBIO", 4) != 0) continue; - printf_debug("Found candidate at: %08lx-%08lx\n", + msg_pdbg("Found candidate at: %08lx-%08lx\n", addr, addr + head->table_bytes); if (head->header_bytes != sizeof(*head)) { - fprintf(stderr, "Header bytes of %d are incorrect.\n", + msg_perr("Header bytes of %d are incorrect.\n", head->header_bytes); continue; } if (count_lb_records(head) != head->table_entries) { - fprintf(stderr, "Bad record count: %d.\n", + msg_perr("Bad record count: %d.\n", head->table_entries); continue; } if (compute_checksum((uint8_t *) head, sizeof(*head)) != 0) { - fprintf(stderr, "Bad header checksum.\n"); + msg_perr("Bad header checksum.\n"); continue; } if (compute_checksum(recs, head->table_bytes) != head->table_checksum) { - fprintf(stderr, "Bad table checksum: %04x.\n", + msg_perr("Bad table checksum: %04x.\n", head->table_checksum); continue; } - printf_debug("Found coreboot table at 0x%08lx.\n", addr); + msg_pdbg("Found coreboot table at 0x%08lx.\n", addr); return head; }; @@ -150,7 +150,7 @@ rec = (struct lb_mainboard *)ptr; max_size = rec->size - sizeof(*rec); - printf("Vendor ID: %.*s, part ID: %.*s\n", + msg_pdbg("Vendor ID: %.*s, part ID: %.*s\n", max_size - rec->vendor_idx, rec->strings + rec->vendor_idx, max_size - rec->part_number_idx, @@ -161,7 +161,7 @@ rec->strings + rec->part_number_idx); if (lb_part) { - printf("Overwritten by command line, vendor ID: %s, part ID: %s.\n", lb_vendor, lb_part); + msg_pdbg("Overwritten by command line, vendor ID: %s, part ID: %s.\n", lb_vendor, lb_part); } else { partvendor_from_cbtable = 1; lb_part = strdup(part); @@ -235,16 +235,16 @@ } if (!lb_table) { - printf("No coreboot table found.\n"); + msg_pinfo("No coreboot table found.\n"); return -1; } addr = ((char *)lb_table) - ((char *)table_area) + start; - fprintf(stdout, "coreboot table found at 0x%lx.\n", + msg_pinfo("coreboot table found at 0x%lx.\n", (unsigned long)lb_table - (unsigned long)table_area + start); rec = (struct lb_record *)(((char *)lb_table) + lb_table->header_bytes); last = (struct lb_record *)(((char *)rec) + lb_table->table_bytes); - printf_debug("coreboot header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n", + msg_pdbg("coreboot header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n", lb_table->header_bytes, lb_table->header_checksum, lb_table->table_bytes, lb_table->table_checksum, lb_table->table_entries); Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/chipset_enable.c Fri May 7 22:09:04 2010 (r997) @@ -74,8 +74,8 @@ pci_write_byte(dev, 0x40, new); newer = pci_read_byte(dev, 0x40); if (newer != new) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); - printf_debug("Stuck at 0x%x\n", newer); + msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); + msg_pinfo("Stuck at 0x%x\n", newer); return -1; } return 0; @@ -91,9 +91,9 @@ if (!sbdev) sbdev = pci_dev_find_vendorclass(vendor, 0x0000); if (!sbdev) - fprintf(stderr, "No southbridge found for %s!\n", name); + msg_perr("No southbridge found for %s!\n", name); if (sbdev) - printf_debug("Found southbridge %04x:%04x at %02x:%02x:%01x\n", + msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n", sbdev->vendor_id, sbdev->device_id, sbdev->bus, sbdev->dev, sbdev->func); return sbdev; @@ -162,8 +162,8 @@ pci_write_byte(sbdev, 0x45, new); newer = pci_read_byte(sbdev, 0x45); if (newer != new) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); - printf_debug("Stuck at 0x%x\n", newer); + msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); + msg_pinfo("Stuck at 0x%x\n", newer); ret = -1; } @@ -188,8 +188,8 @@ pci_write_byte(sbdev, 0x45, new); newer = pci_read_byte(sbdev, 0x45); if (newer != new) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); - printf_debug("Stuck at 0x%x\n", newer); + msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); + msg_pinfo("Stuck at 0x%x\n", newer); ret = -1; } @@ -235,7 +235,7 @@ pci_write_word(dev, xbcs, new); if (pci_read_word(dev, xbcs) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name); + msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name); return -1; } @@ -257,11 +257,11 @@ */ old = pci_read_byte(dev, bios_cntl); - printf_debug("\nBIOS Lock Enable: %sabled, ", + msg_pdbg("\nBIOS Lock Enable: %sabled, ", (old & (1 << 1)) ? "en" : "dis"); - printf_debug("BIOS Write Enable: %sabled, ", + msg_pdbg("BIOS Write Enable: %sabled, ", (old & (1 << 0)) ? "en" : "dis"); - printf_debug("BIOS_CNTL is 0x%x\n", old); + msg_pdbg("BIOS_CNTL is 0x%x\n", old); new = old | 1; @@ -271,7 +271,7 @@ pci_write_byte(dev, bios_cntl, new); if (pci_read_byte(dev, bios_cntl) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name); + msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name); return -1; } @@ -306,7 +306,7 @@ fwh_conf = (uint32_t)strtoul(idsel, NULL, 0); /* FIXME: Need to undo this on shutdown. */ - printf("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf); + msg_pinfo("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf); pci_write_long(dev, 0xd0, fwh_conf); pci_write_word(dev, 0xd4, fwh_conf); /* FIXME: Decode settings are not changed. */ @@ -321,7 +321,7 @@ fwh_conf = pci_read_long(dev, 0xd0); for (i = 7; i >= 0; i--) { tmp = (fwh_conf >> (i * 4)) & 0xf; - printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x", + msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x", (0x1ff8 + i) * 0x80000, (0x1ff0 + i) * 0x80000, tmp); @@ -335,7 +335,7 @@ fwh_conf = pci_read_word(dev, 0xd4); for (i = 3; i >= 0; i--) { tmp = (fwh_conf >> (i * 4)) & 0xf; - printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x", + msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x", (0xff4 + i) * 0x100000, (0xff0 + i) * 0x100000, tmp); @@ -350,7 +350,7 @@ fwh_conf = pci_read_word(dev, 0xd8); for (i = 7; i >= 0; i--) { tmp = (fwh_conf >> (i + 0x8)) & 0x1; - printf_debug("\n0x%08x/0x%08x FWH decode %sabled", + msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled", (0x1ff8 + i) * 0x80000, (0x1ff0 + i) * 0x80000, tmp ? "en" : "dis"); @@ -362,7 +362,7 @@ } for (i = 3; i >= 0; i--) { tmp = (fwh_conf >> i) & 0x1; - printf_debug("\n0x%08x/0x%08x FWH decode %sabled", + msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled", (0xff4 + i) * 0x100000, (0xff0 + i) * 0x100000, tmp ? "en" : "dis"); @@ -373,7 +373,7 @@ } } max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); - printf_debug("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); + msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); /* If we're called by enable_flash_ich_dc_spi, it will override * buses_supported anyway. @@ -391,7 +391,7 @@ return err; old = pci_read_byte(dev, 0xd9); - printf_debug("BIOS Prefetch Enable: %sabled, ", + msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis"); new = old & ~1; @@ -413,10 +413,10 @@ /* Do we really need no write enable? */ mmio_base = (pci_read_long(dev, 0xbc)) << 8; - printf_debug("MMIO base at = 0x%x\n", mmio_base); + msg_pdbg("MMIO base at = 0x%x\n", mmio_base); spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); - printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", + msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", mmio_readw(spibar + 0x6c)); /* Not sure if it speaks all these bus protocols. */ @@ -444,20 +444,20 @@ /* Get physical address of Root Complex Register Block */ tmp = pci_read_long(dev, 0xf0) & 0xffffc000; - printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp); + msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp); /* Map RCBA to virtual memory */ rcrb = physmap("ICH RCRB", tmp, 0x4000); gcs = mmio_readl(rcrb + 0x3410); - printf_debug("GCS = 0x%x: ", gcs); - printf_debug("BIOS Interface Lock-Down: %sabled, ", + msg_pdbg("GCS = 0x%x: ", gcs); + msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); bbs = (gcs >> 10) & 0x3; - printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); + msg_pdbg("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); buc = mmio_readb(rcrb + 0x3414); - printf_debug("Top Swap : %s\n", + msg_pdbg("Top Swap : %s\n", (buc & 1) ? "enabled (A16 inverted)" : "not enabled"); /* It seems the ICH7 does not support SPI and LPC chips at the same @@ -492,105 +492,105 @@ } /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ - printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); + msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); /* Assign Virtual Address */ spibar = rcrb + spibar_offset; switch (spi_controller) { case SPI_CONTROLLER_ICH7: - printf_debug("0x00: 0x%04x (SPIS)\n", + msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(spibar + 0)); - printf_debug("0x02: 0x%04x (SPIC)\n", + msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(spibar + 2)); - printf_debug("0x04: 0x%08x (SPIA)\n", + msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(spibar + 4)); for (i = 0; i < 8; i++) { int offs; offs = 8 + (i * 8); - printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, + msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, mmio_readl(spibar + offs), i); - printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, + msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, mmio_readl(spibar + offs + 4), i); } - printf_debug("0x50: 0x%08x (BBAR)\n", + msg_pdbg("0x50: 0x%08x (BBAR)\n", mmio_readl(spibar + 0x50)); - printf_debug("0x54: 0x%04x (PREOP)\n", + msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(spibar + 0x54)); - printf_debug("0x56: 0x%04x (OPTYPE)\n", + msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(spibar + 0x56)); - printf_debug("0x58: 0x%08x (OPMENU)\n", + msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(spibar + 0x58)); - printf_debug("0x5c: 0x%08x (OPMENU+4)\n", + msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(spibar + 0x5c)); for (i = 0; i < 4; i++) { int offs; offs = 0x60 + (i * 4); - printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, + msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, mmio_readl(spibar + offs), i); } - printf_debug("\n"); + msg_pdbg("\n"); if (mmio_readw(spibar) & (1 << 15)) { - printf("WARNING: SPI Configuration Lockdown activated.\n"); + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } ich_init_opcodes(); break; case SPI_CONTROLLER_ICH9: tmp2 = mmio_readw(spibar + 4); - printf_debug("0x04: 0x%04x (HSFS)\n", tmp2); - printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1)); - printf_debug("FDV %i, ", (tmp2 >> 14) & 1); - printf_debug("FDOPSS %i, ", (tmp2 >> 13) & 1); - printf_debug("SCIP %i, ", (tmp2 >> 5) & 1); - printf_debug("BERASE %i, ", (tmp2 >> 3) & 3); - printf_debug("AEL %i, ", (tmp2 >> 2) & 1); - printf_debug("FCERR %i, ", (tmp2 >> 1) & 1); - printf_debug("FDONE %i\n", (tmp2 >> 0) & 1); + msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); + msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); + msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); + msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); + msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); + msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); + msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); + msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); + msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); tmp = mmio_readl(spibar + 0x50); - printf_debug("0x50: 0x%08x (FRAP)\n", tmp); - printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff); - printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff); - printf_debug("BRWA %i, ", (tmp >> 8) & 0xff); - printf_debug("BRRA %i\n", (tmp >> 0) & 0xff); + msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); + msg_pdbg("BMWAG %i, ", (tmp >> 24) & 0xff); + msg_pdbg("BMRAG %i, ", (tmp >> 16) & 0xff); + msg_pdbg("BRWA %i, ", (tmp >> 8) & 0xff); + msg_pdbg("BRRA %i\n", (tmp >> 0) & 0xff); - printf_debug("0x54: 0x%08x (FREG0)\n", + msg_pdbg("0x54: 0x%08x (FREG0)\n", mmio_readl(spibar + 0x54)); - printf_debug("0x58: 0x%08x (FREG1)\n", + msg_pdbg("0x58: 0x%08x (FREG1)\n", mmio_readl(spibar + 0x58)); - printf_debug("0x5C: 0x%08x (FREG2)\n", + msg_pdbg("0x5C: 0x%08x (FREG2)\n", mmio_readl(spibar + 0x5C)); - printf_debug("0x60: 0x%08x (FREG3)\n", + msg_pdbg("0x60: 0x%08x (FREG3)\n", mmio_readl(spibar + 0x60)); - printf_debug("0x64: 0x%08x (FREG4)\n", + msg_pdbg("0x64: 0x%08x (FREG4)\n", mmio_readl(spibar + 0x64)); - printf_debug("0x74: 0x%08x (PR0)\n", + msg_pdbg("0x74: 0x%08x (PR0)\n", mmio_readl(spibar + 0x74)); - printf_debug("0x78: 0x%08x (PR1)\n", + msg_pdbg("0x78: 0x%08x (PR1)\n", mmio_readl(spibar + 0x78)); - printf_debug("0x7C: 0x%08x (PR2)\n", + msg_pdbg("0x7C: 0x%08x (PR2)\n", mmio_readl(spibar + 0x7C)); - printf_debug("0x80: 0x%08x (PR3)\n", + msg_pdbg("0x80: 0x%08x (PR3)\n", mmio_readl(spibar + 0x80)); - printf_debug("0x84: 0x%08x (PR4)\n", + msg_pdbg("0x84: 0x%08x (PR4)\n", mmio_readl(spibar + 0x84)); - printf_debug("0x90: 0x%08x (SSFS, SSFC)\n", + msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", mmio_readl(spibar + 0x90)); - printf_debug("0x94: 0x%04x (PREOP)\n", + msg_pdbg("0x94: 0x%04x (PREOP)\n", mmio_readw(spibar + 0x94)); - printf_debug("0x96: 0x%04x (OPTYPE)\n", + msg_pdbg("0x96: 0x%04x (OPTYPE)\n", mmio_readw(spibar + 0x96)); - printf_debug("0x98: 0x%08x (OPMENU)\n", + msg_pdbg("0x98: 0x%08x (OPMENU)\n", mmio_readl(spibar + 0x98)); - printf_debug("0x9C: 0x%08x (OPMENU+4)\n", + msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(spibar + 0x9C)); - printf_debug("0xA0: 0x%08x (BBAR)\n", + msg_pdbg("0xA0: 0x%08x (BBAR)\n", mmio_readl(spibar + 0xA0)); - printf_debug("0xB0: 0x%08x (FDOC)\n", + msg_pdbg("0xB0: 0x%08x (FDOC)\n", mmio_readl(spibar + 0xB0)); if (tmp2 & (1 << 15)) { - printf("WARNING: SPI Configuration Lockdown activated.\n"); + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } ich_init_opcodes(); @@ -601,18 +601,18 @@ } old = pci_read_byte(dev, 0xdc); - printf_debug("SPI Read Configuration: "); + msg_pdbg("SPI Read Configuration: "); new = (old >> 2) & 0x3; switch (new) { case 0: case 1: case 2: - printf_debug("prefetching %sabled, caching %sabled, ", + msg_pdbg("prefetching %sabled, caching %sabled, ", (new & 0x2) ? "en" : "dis", (new & 0x1) ? "dis" : "en"); break; default: - printf_debug("invalid prefetching/caching settings, "); + msg_pdbg("invalid prefetching/caching settings, "); break; } @@ -652,7 +652,7 @@ pci_write_byte(dev, 0x40, val); if (pci_read_byte(dev, 0x40) != val) { - printf("\nWARNING: Failed to enable flash write on \"%s\"\n", + msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n", name); return -1; } @@ -769,7 +769,7 @@ new = pci_read_byte(dev, 0x52); if (new != 0xee) { - printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name); + msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name); return -1; } @@ -787,7 +787,7 @@ if (new != old) { pci_write_byte(dev, 0x43, new); if (pci_read_byte(dev, 0x43) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name); + msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name); } } @@ -799,7 +799,7 @@ pci_write_byte(dev, 0x40, new); if (pci_read_byte(dev, 0x40) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); + msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); return -1; } @@ -819,7 +819,7 @@ /* No protection flags for this region?*/ if ((prot & 0x3) == 0) continue; - printf_debug("SB600 %s%sprotected from %u to %u\n", + msg_pinfo("SB600 %s%sprotected from %u to %u\n", (prot & 0x1) ? "write " : "", (prot & 0x2) ? "read " : "", (prot & 0xfffffc00), @@ -828,7 +828,7 @@ pci_write_byte(dev, reg, prot); prot = pci_read_long(dev, reg); if (prot & 0x3) - printf("SB600 %s%sunprotect failed from %u to %u\n", + msg_perr("SB600 %s%sunprotect failed from %u to %u\n", (prot & 0x1) ? "write " : "", (prot & 0x2) ? "read " : "", (prot & 0xfffffc00), @@ -838,7 +838,7 @@ /* Read SPI_BaseAddr */ tmp = pci_read_long(dev, 0xa0); tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ - printf_debug("SPI base address is at 0x%x\n", tmp); + msg_pdbg("SPI base address is at 0x%x\n", tmp); /* If the BAR has address 0, it is unlikely SPI is used. */ if (!tmp) @@ -854,17 +854,17 @@ sb600_spibar += tmp & 0xfff; tmp = pci_read_long(dev, 0xa0); - printf_debug("AltSpiCSEnable=%i, SpiRomEnable=%i, " + msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, (tmp & 0x4) >> 2); tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; - printf_debug("PrefetchEnSPIFromIMC=%i, ", tmp); + msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); tmp = pci_read_byte(dev, 0xbb); - printf_debug("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", + msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", tmp & 0x1, (tmp & 0x20) >> 5); tmp = mmio_readl(sb600_spibar); - printf_debug("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " + msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, @@ -876,7 +876,7 @@ smbus_dev = pci_dev_find(0x1002, 0x4385); if (has_spi && !smbus_dev) { - fprintf(stderr, "ERROR: SMBus device not found. Not enabling SPI.\n"); + msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); has_spi = 0; } if (has_spi) { @@ -884,22 +884,22 @@ /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ reg = pci_read_byte(smbus_dev, 0xAB); reg &= 0xC0; - printf_debug("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); - printf_debug("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); + msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); + msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); if (reg != 0x00) has_spi = 0; /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ reg = pci_read_byte(smbus_dev, 0x83); reg &= 0xC0; - printf_debug("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); - printf_debug("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); + msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); + msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); /* SPI_HOLD is not used on all boards, filter it out. */ if ((reg & 0x80) != 0x00) has_spi = 0; /* GPIO47/SPI_CLK status */ reg = pci_read_byte(smbus_dev, 0xA7); reg &= 0x40; - printf_debug("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); + msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); if (reg != 0x00) has_spi = 0; } @@ -914,24 +914,24 @@ OUTB(0x8f, 0xcd6); reg = INB(0xcd7); reg &= 0x0e; - printf_debug("ROM strap override is %sactive", (reg & 0x02) ? "" : "not "); + msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not "); if (reg & 0x02) { switch ((reg & 0x0c) >> 2) { case 0x00: - printf_debug(": LPC"); + msg_pdbg(": LPC"); break; case 0x01: - printf_debug(": PCI"); + msg_pdbg(": PCI"); break; case 0x02: - printf_debug(": FWH"); + msg_pdbg(": FWH"); break; case 0x03: - printf_debug(": SPI"); + msg_pdbg(": SPI"); break; } } - printf_debug("\n"); + msg_pdbg("\n"); /* Force enable SPI ROM in SB600 PM register. * If we enable SPI ROM here, we have to disable it after we leave. @@ -970,7 +970,7 @@ if (new != old) { pci_write_byte(dev, 0x88, new); if (pci_read_byte(dev, 0x88) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name); + msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name); } } @@ -981,7 +981,7 @@ pci_write_byte(dev, 0x6d, new); if (pci_read_byte(dev, 0x6d) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); + msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); return -1; } @@ -998,7 +998,7 @@ smbusdev = pci_dev_find(0x1002, 0x4372); if (!smbusdev) { - fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n"); + msg_perr("ERROR: SMBus device not found. Aborting.\n"); exit(1); } @@ -1047,7 +1047,7 @@ pci_write_byte(dev, 0x6d, new); if (pci_read_byte(dev, 0x6d) != new) { - printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); + msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); return -1; } @@ -1277,7 +1277,7 @@ flashbase = parx << 12; } } else { - printf("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n"); + msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n"); } /* 4. Clean up */ @@ -1436,18 +1436,18 @@ } if (dev) { - printf("Found chipset \"%s %s\", enabling flash write... ", + msg_pinfo("Found chipset \"%s %s\", enabling flash write... ", chipset_enables[i].vendor_name, chipset_enables[i].device_name); ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name); if (ret) - printf("FAILED!\n"); + msg_pinfo("FAILED!\n"); else - printf("OK.\n"); + msg_pinfo("OK.\n"); } - printf("This chipset supports the following protocols: %s.\n", + msg_pinfo("This chipset supports the following protocols: %s.\n", flashbuses_to_text(buses_supported)); return ret; Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/dmi.c Fri May 7 22:09:04 2010 (r997) @@ -53,12 +53,12 @@ "%s -s %s", dmidecode_command, string_name); dmidecode_pipe = popen(commandline, "r"); if (!dmidecode_pipe) { - printf_debug("DMI pipe open error\n"); + msg_perr("DMI pipe open error\n"); return NULL; } if (!fgets(answerbuf, DMI_MAX_ANSWER_LEN, dmidecode_pipe)) { if(ferror(dmidecode_pipe)) { - printf_debug("DMI pipe read error\n"); + msg_perr("DMI pipe read error\n"); pclose(dmidecode_pipe); return NULL; } else { @@ -70,7 +70,8 @@ while (!feof(dmidecode_pipe)) getc(dmidecode_pipe); if (pclose(dmidecode_pipe) != 0) { - printf_debug("DMI pipe close error\n"); + msg_pinfo("dmidecode execution unsucessfull - continuing " + "without DMI info\n"); return NULL; } @@ -78,7 +79,7 @@ if (answerbuf[0] != 0 && answerbuf[strlen(answerbuf) - 1] == '\n') answerbuf[strlen(answerbuf) - 1] = 0; - printf_debug("DMI string %s: \"%s\"\n", string_name, answerbuf); + msg_pdbg("DMI string %s: \"%s\"\n", string_name, answerbuf); result = strdup(answerbuf); if (!result) @@ -104,7 +105,7 @@ chassis_type = get_dmi_string("chassis-type"); if (chassis_type && (!strcmp(chassis_type, "Notebook") || !strcmp(chassis_type, "Portable"))) { - printf_debug("Laptop detected via DMI\n"); + msg_pdbg("Laptop detected via DMI\n"); is_laptop = 1; } free(chassis_type); @@ -126,7 +127,7 @@ int anchored = 0; int patternlen; - printf_debug("matching %s against %s\n", value, pattern); + msg_pspew("matching %s against %s\n", value, pattern); /* The empty string is part of all strings! */ if (pattern[0] == 0) return 1; Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/flashrom.c Fri May 7 22:09:04 2010 (r997) @@ -520,7 +520,7 @@ if (devlen) { dev = malloc(devlen + 1); if (!dev) { - fprintf(stderr, "Out of memory!\n"); + msg_gerr("Out of memory!\n"); exit(1); } strncpy(dev, param_pos, devlen); @@ -532,7 +532,7 @@ memmove(param_pos, rest, strlen(rest) + 1); tmp = realloc(*haystack, strlen(*haystack) + 1); if (!tmp) { - fprintf(stderr, "Out of memory!\n"); + msg_gerr("Out of memory!\n"); exit(1); } *haystack = tmp; @@ -549,7 +549,7 @@ uint8_t *cmpbuf = malloc(len); if (!cmpbuf) { - fprintf(stderr, "Could not allocate memory!\n"); + msg_gerr("Could not allocate memory!\n"); exit(1); } memset(cmpbuf, 0xff, len); @@ -577,16 +577,16 @@ goto out_free; if (!flash->read) { - fprintf(stderr, "ERROR: flashrom has no read function for this flash chip.\n"); + msg_cerr("ERROR: flashrom has no read function for this flash chip.\n"); return 1; } if (!readbuf) { - fprintf(stderr, "Could not allocate memory!\n"); + msg_gerr("Could not allocate memory!\n"); exit(1); } if (start + len > flash->total_size * 1024) { - fprintf(stderr, "Error: %s called with start 0x%x + len 0x%x >" + msg_gerr("Error: %s called with start 0x%x + len 0x%x >" " total_size 0x%x\n", __func__, start, len, flash->total_size * 1024); ret = -1; @@ -614,7 +614,7 @@ if (cmpbuf[starthere - start + j] != readbuf[j]) { /* Only print the first failure. */ if (!failcount++) - fprintf(stderr, "%s FAILED at 0x%08x! " + msg_cerr("%s FAILED at 0x%08x! " "Expected=0x%02x, Read=0x%02x,", message, starthere + j, cmpbuf[starthere - start + j], @@ -623,7 +623,7 @@ } } if (failcount) { - fprintf(stderr, " failed byte count from 0x%08x-0x%08x: 0x%x\n", + msg_cerr(" failed byte count from 0x%08x-0x%08x: 0x%x\n", start, start + len - 1, failcount); ret = -1; } @@ -748,7 +748,7 @@ int i; if (!buf) { - fprintf(stderr, "Invalid buffer!\n"); + msg_gerr("Invalid buffer!\n"); return 1; } @@ -836,7 +836,7 @@ if ((buses & CHIP_BUSTYPE_PARALLEL) && (max_rom_decode.parallel < size)) { limitexceeded++; - printf_debug("Chip size %u kB is bigger than supported " + msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, @@ -844,7 +844,7 @@ } if ((buses & CHIP_BUSTYPE_LPC) && (max_rom_decode.lpc < size)) { limitexceeded++; - printf_debug("Chip size %u kB is bigger than supported " + msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, @@ -852,7 +852,7 @@ } if ((buses & CHIP_BUSTYPE_FWH) && (max_rom_decode.fwh < size)) { limitexceeded++; - printf_debug("Chip size %u kB is bigger than supported " + msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, @@ -860,7 +860,7 @@ } if ((buses & CHIP_BUSTYPE_SPI) && (max_rom_decode.spi < size)) { limitexceeded++; - printf_debug("Chip size %u kB is bigger than supported " + msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, @@ -873,7 +873,7 @@ */ if (bitcount(buses) > limitexceeded) /* FIXME: This message is designed towards CLI users. */ - printf_debug("There is at least one common chip/programmer " + msg_pdbg("There is at least one common chip/programmer " "interface which can support a chip of this size. " "You can try --force at your own risk.\n"); return 1; @@ -934,7 +934,7 @@ if (!flash || !flash->name) return NULL; - printf("%s chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n", + msg_cinfo("%s chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n", force ? "Assuming" : "Found", flash->vendor, flash->name, flash->total_size, flashbuses_to_text(flash->bustype), base); @@ -950,12 +950,12 @@ int ret; int total_size = flash->total_size * 1024; - printf("Verifying flash... "); + msg_cinfo("Verifying flash... "); ret = verify_range(flash, buf, 0, total_size, NULL); if (!ret) - printf("VERIFIED. \n"); + msg_cinfo("VERIFIED. \n"); return ret; } @@ -968,17 +968,17 @@ unsigned char *buf = calloc(size, sizeof(char)); if (!filename) { - printf("Error: No filename specified.\n"); + msg_gerr("Error: No filename specified.\n"); return 1; } if ((image = fopen(filename, "wb")) == NULL) { perror(filename); exit(1); } - printf("Reading flash... "); + msg_cinfo("Reading flash... "); if (!flash->read) { - printf("FAILED!\n"); - fprintf(stderr, "ERROR: flashrom has no read function for this flash chip.\n"); + msg_cinfo("FAILED!\n"); + msg_cerr("ERROR: flashrom has no read function for this flash chip.\n"); return 1; } else flash->read(flash, buf, 0, size); @@ -986,7 +986,7 @@ numbytes = fwrite(buf, 1, size, image); fclose(image); free(buf); - printf("%s.\n", numbytes == size ? "done" : "FAILED"); + msg_cinfo("%s.\n", numbytes == size ? "done" : "FAILED"); if (numbytes != size) return 1; return 0; @@ -1028,7 +1028,7 @@ } /* Empty eraseblock definition with erase function. */ if (!done && eraser.block_erase) - msg_pspew("Strange: Empty eraseblock definition with " + msg_gspew("Strange: Empty eraseblock definition with " "non-empty erase function. Not an error.\n"); if (!done) continue; @@ -1065,31 +1065,31 @@ int i, j, k, ret = 0, found = 0; unsigned int start, len; - printf("Erasing flash chip... "); + msg_cinfo("Erasing flash chip... "); for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { unsigned int done = 0; struct block_eraser eraser = flash->block_erasers[k]; - printf_debug("Looking at blockwise erase function %i... ", k); + msg_cdbg("Looking at blockwise erase function %i... ", k); if (!eraser.block_erase && !eraser.eraseblocks[0].count) { - printf_debug("not defined. " + msg_cdbg("not defined. " "Looking for another erase function.\n"); continue; } if (!eraser.block_erase && eraser.eraseblocks[0].count) { - printf_debug("eraseblock layout is known, but no " + msg_cdbg("eraseblock layout is known, but no " "matching block erase function found. " "Looking for another erase function.\n"); continue; } if (eraser.block_erase && !eraser.eraseblocks[0].count) { - printf_debug("block erase function found, but " + msg_cdbg("block erase function found, but " "eraseblock layout is unknown. " "Looking for another erase function.\n"); continue; } found = 1; - printf_debug("trying... "); + msg_cdbg("trying... "); for (i = 0; i < NUM_ERASEREGIONS; i++) { /* count==0 for all automatically initialized array * members so the loop below won't be executed for them. @@ -1097,7 +1097,7 @@ for (j = 0; j < eraser.eraseblocks[i].count; j++) { start = done + eraser.eraseblocks[i].size * j; len = eraser.eraseblocks[i].size; - printf_debug("0x%06x-0x%06x, ", start, + msg_cdbg("0x%06x-0x%06x, ", start, start + len - 1); ret = eraser.block_erase(flash, start, len); if (ret) @@ -1108,27 +1108,27 @@ done += eraser.eraseblocks[i].count * eraser.eraseblocks[i].size; } - printf_debug("\n"); + msg_cdbg("\n"); /* If everything is OK, don't try another erase function. */ if (!ret) break; } if (!found) { - fprintf(stderr, "ERROR: flashrom has no erase function for this flash chip.\n"); + msg_cerr("ERROR: flashrom has no erase function for this flash chip.\n"); return 1; } if (ret) { - fprintf(stderr, "FAILED!\n"); + msg_cerr("FAILED!\n"); } else { - printf("SUCCESS.\n"); + msg_cinfo("SUCCESS.\n"); } return ret; } void emergency_help_message(void) { - fprintf(stderr, "Your flash chip is in an unknown state.\n" + msg_gerr("Your flash chip is in an unknown state.\n" "Get help on IRC at irc.freenode.net (channel #flashrom) or\n" "mail flashrom(a)flashrom.org!\n--------------------" "-----------------------------------------------------------\n" @@ -1140,11 +1140,11 @@ { enum programmer p; for (p = 0; p < PROGRAMMER_INVALID; p++) { - printf("%s", programmer_table[p].name); + msg_ginfo("%s", programmer_table[p].name); if (p < PROGRAMMER_INVALID - 1) - printf("%s", delim); + msg_ginfo("%s", delim); } - printf("\n"); + msg_ginfo("\n"); } void print_sysinfo(void) @@ -1183,7 +1183,7 @@ void print_version(void) { - printf("flashrom v%s", flashrom_version); + msg_ginfo("flashrom v%s\n", flashrom_version); print_sysinfo(); } @@ -1196,16 +1196,16 @@ * if more errors exist. */ if (ARRAY_SIZE(programmer_table) - 1 != PROGRAMMER_INVALID) { - fprintf(stderr, "Programmer table miscompilation!\n"); + msg_gerr("Programmer table miscompilation!\n"); ret = 1; } if (spi_programmer_count - 1 != SPI_CONTROLLER_INVALID) { - fprintf(stderr, "SPI programmer table miscompilation!\n"); + msg_gerr("SPI programmer table miscompilation!\n"); ret = 1; } #if BITBANG_SPI_SUPPORT == 1 if (bitbang_spi_master_count - 1 != BITBANG_SPI_INVALID) { - fprintf(stderr, "Bitbanging SPI master table miscompilation!\n"); + msg_gerr("Bitbanging SPI master table miscompilation!\n"); ret = 1; } #endif @@ -1218,36 +1218,36 @@ void check_chip_supported(struct flashchip *flash) { if (TEST_OK_MASK != (flash->tested & TEST_OK_MASK)) { - printf("===\n"); + msg_cinfo("===\n"); if (flash->tested & TEST_BAD_MASK) { - printf("This flash part has status NOT WORKING for operations:"); + msg_cinfo("This flash part has status NOT WORKING for operations:"); if (flash->tested & TEST_BAD_PROBE) - printf(" PROBE"); + msg_cinfo(" PROBE"); if (flash->tested & TEST_BAD_READ) - printf(" READ"); + msg_cinfo(" READ"); if (flash->tested & TEST_BAD_ERASE) - printf(" ERASE"); + msg_cinfo(" ERASE"); if (flash->tested & TEST_BAD_WRITE) - printf(" WRITE"); - printf("\n"); + msg_cinfo(" WRITE"); + msg_cinfo("\n"); } if ((!(flash->tested & TEST_BAD_PROBE) && !(flash->tested & TEST_OK_PROBE)) || (!(flash->tested & TEST_BAD_READ) && !(flash->tested & TEST_OK_READ)) || (!(flash->tested & TEST_BAD_ERASE) && !(flash->tested & TEST_OK_ERASE)) || (!(flash->tested & TEST_BAD_WRITE) && !(flash->tested & TEST_OK_WRITE))) { - printf("This flash part has status UNTESTED for operations:"); + msg_cinfo("This flash part has status UNTESTED for operations:"); if (!(flash->tested & TEST_BAD_PROBE) && !(flash->tested & TEST_OK_PROBE)) - printf(" PROBE"); + msg_cinfo(" PROBE"); if (!(flash->tested & TEST_BAD_READ) && !(flash->tested & TEST_OK_READ)) - printf(" READ"); + msg_cinfo(" READ"); if (!(flash->tested & TEST_BAD_ERASE) && !(flash->tested & TEST_OK_ERASE)) - printf(" ERASE"); + msg_cinfo(" ERASE"); if (!(flash->tested & TEST_BAD_WRITE) && !(flash->tested & TEST_OK_WRITE)) - printf(" WRITE"); - printf("\n"); + msg_cinfo(" WRITE"); + msg_cinfo("\n"); } /* FIXME: This message is designed towards CLI users. */ - printf("Please email a report to flashrom(a)flashrom.org if any " + msg_cinfo("Please email a report to flashrom(a)flashrom.org if any " "of the above operations\nwork correctly for you with " "this flash part. Please include the flashrom\noutput " "with the additional -V option for all operations you " @@ -1278,13 +1278,13 @@ if (erase_it) { if (flash->tested & TEST_BAD_ERASE) { - fprintf(stderr, "Erase is not working on this chip. "); + msg_cerr("Erase is not working on this chip. "); if (!force) { - fprintf(stderr, "Aborting.\n"); + msg_cerr("Aborting.\n"); programmer_shutdown(); return 1; } else { - fprintf(stderr, "Continuing anyway.\n"); + msg_cerr("Continuing anyway.\n"); } } if (flash->unlock) @@ -1310,24 +1310,24 @@ flash->unlock(flash); if (flash->tested & TEST_BAD_ERASE) { - fprintf(stderr, "Erase is not working on this chip " + msg_cerr("Erase is not working on this chip " "and erase is needed for write. "); if (!force) { - fprintf(stderr, "Aborting.\n"); + msg_cerr("Aborting.\n"); programmer_shutdown(); return 1; } else { - fprintf(stderr, "Continuing anyway.\n"); + msg_cerr("Continuing anyway.\n"); } } if (flash->tested & TEST_BAD_WRITE) { - fprintf(stderr, "Write is not working on this chip. "); + msg_cerr("Write is not working on this chip. "); if (!force) { - fprintf(stderr, "Aborting.\n"); + msg_cerr("Aborting.\n"); programmer_shutdown(); return 1; } else { - fprintf(stderr, "Continuing anyway.\n"); + msg_cerr("Continuing anyway.\n"); } } if ((image = fopen(filename, "rb")) == NULL) { @@ -1341,7 +1341,7 @@ exit(1); } if (image_stat.st_size != flash->total_size * 1024) { - fprintf(stderr, "Error: Image size doesn't match\n"); + msg_gerr("Error: Image size doesn't match\n"); programmer_shutdown(); exit(1); } @@ -1352,7 +1352,7 @@ #endif fclose(image); if (numbytes != size) { - fprintf(stderr, "Error: Failed to read file. Got %ld bytes, wanted %ld!\n", numbytes, size); + msg_gerr("Error: Failed to read file. Got %ld bytes, wanted %ld!\n", numbytes, size); programmer_shutdown(); return 1; } @@ -1365,20 +1365,20 @@ // //////////////////////////////////////////////////////////// if (write_it) { - printf("Writing flash chip... "); + msg_cinfo("Writing flash chip... "); if (!flash->write) { - fprintf(stderr, "Error: flashrom has no write function for this flash chip.\n"); + msg_cerr("Error: flashrom has no write function for this flash chip.\n"); programmer_shutdown(); return 1; } ret = flash->write(flash, buf); if (ret) { - fprintf(stderr, "FAILED!\n"); + msg_cerr("FAILED!\n"); emergency_help_message(); programmer_shutdown(); return 1; } else { - printf("COMPLETE.\n"); + msg_cinfo("COMPLETE.\n"); } } Modified: trunk/hwaccess.c ============================================================================== --- trunk/hwaccess.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/hwaccess.c Fri May 7 22:09:04 2010 (r997) @@ -41,7 +41,7 @@ #else if (iopl(3) != 0) { #endif - fprintf(stderr, "ERROR: Could not get I/O privileges (%s).\n" + msg_perr("ERROR: Could not get I/O privileges (%s).\n" "You need to be root.\n", strerror(errno)); exit(1); } Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/ichspi.c Fri May 7 22:09:04 2010 (r997) @@ -38,17 +38,6 @@ #include "chipdrivers.h" #include "spi.h" -/* Change this to #define if you want lowlevel debugging of commands - * sent to the ICH/VIA SPI controller. - */ -#undef COMM_DEBUG - -#ifdef COMM_DEBUG -#define msg_comm_debug printf_debug -#else -#define msg_comm_debug(...) do {} while (0) -#endif - /* ICH9 controller register definition */ #define ICH9_REG_FADDR 0x08 /* 32 Bits */ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ @@ -237,7 +226,7 @@ uint32_t opmenu[2]; if (op == NULL) { - printf_debug("\n%s: null OPCODES pointer!\n", __func__); + msg_perr("\n%s: null OPCODES pointer!\n", __func__); return -1; } @@ -256,7 +245,7 @@ opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4); break; default: - printf_debug("%s: unsupported chipset\n", __func__); + msg_perr("%s: unsupported chipset\n", __func__); return -1; } @@ -315,7 +304,7 @@ opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8); } - printf_debug("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); + msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); switch (spi_controller) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: @@ -331,7 +320,7 @@ REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]); break; default: - printf_debug("%s: unsupported chipset\n", __func__); + msg_perr("%s: unsupported chipset\n", __func__); return -1; } @@ -352,22 +341,22 @@ return 0; if (ichspi_lock) { - printf_debug("Generating OPCODES... "); + msg_pdbg("Generating OPCODES... "); curopcodes_done = &O_EXISTING; rc = generate_opcodes(curopcodes_done); } else { - printf_debug("Programming OPCODES... "); + msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; rc = program_opcodes(curopcodes_done); } if (rc) { curopcodes = NULL; - printf_debug("failed\n"); + msg_perr("failed\n"); return 1; } else { curopcodes = curopcodes_done; - printf_debug("done\n"); + msg_pdbg("done\n"); return 0; } } @@ -439,7 +428,7 @@ opmenu >>= 8; } if (opcode_index == 8) { - printf_debug("Opcode %x not found.\n", op.opcode); + msg_pdbg("Opcode %x not found.\n", op.opcode); return 1; } temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4; @@ -468,11 +457,12 @@ programmer_delay(10); } if (!timeout) { - printf_debug("timeout\n"); + msg_perr("timeout\n"); } + /* FIXME: make sure we do not needlessly cause transaction errors. */ if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) { - printf_debug("Transaction error!\n"); + msg_pdbg("Transaction error!\n"); return 1; } @@ -557,7 +547,7 @@ opmenu >>= 8; } if (opcode_index == 8) { - printf_debug("Opcode %x not found.\n", op.opcode); + msg_pdbg("Opcode %x not found.\n", op.opcode); return 1; } temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4); @@ -586,11 +576,12 @@ programmer_delay(10); } if (!timeout) { - printf_debug("timeout\n"); + msg_perr("timeout\n"); } + /* FIXME make sure we do not needlessly cause transaction errors. */ if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) { - printf_debug("Transaction error!\n"); + msg_pdbg("Transaction error!\n"); return 1; } @@ -615,7 +606,7 @@ switch (spi_controller) { case SPI_CONTROLLER_VIA: if (datalength > 16) { - fprintf(stderr, "%s: Internal command size error for " + msg_perr("%s: Internal command size error for " "opcode 0x%02x, got datalength=%i, want <=16\n", __func__, op.opcode, datalength); return SPI_INVALID_LENGTH; @@ -623,7 +614,7 @@ return ich7_run_opcode(op, offset, datalength, data, 16); case SPI_CONTROLLER_ICH7: if (datalength > 64) { - fprintf(stderr, "%s: Internal command size error for " + msg_perr("%s: Internal command size error for " "opcode 0x%02x, got datalength=%i, want <=16\n", __func__, op.opcode, datalength); return SPI_INVALID_LENGTH; @@ -631,14 +622,14 @@ return ich7_run_opcode(op, offset, datalength, data, 64); case SPI_CONTROLLER_ICH9: if (datalength > 64) { - fprintf(stderr, "%s: Internal command size error for " + msg_perr("%s: Internal command size error for " "opcode 0x%02x, got datalength=%i, want <=16\n", __func__, op.opcode, datalength); return SPI_INVALID_LENGTH; } return ich9_run_opcode(op, offset, datalength, data); default: - printf_debug("%s: unsupported chipset\n", __func__); + msg_perr("%s: unsupported chipset\n", __func__); } /* If we ever get here, something really weird happened */ @@ -652,14 +643,14 @@ uint32_t remaining = page_size; int towrite; - msg_comm_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n", + msg_pspew("ich_spi_write_page: offset=%d, number=%d, buf=%p\n", offset, page_size, bytes); for (; remaining > 0; remaining -= towrite) { towrite = min(remaining, maxdata); if (spi_nbyte_program(offset + (page_size - remaining), &bytes[page_size - remaining], towrite)) { - printf_debug("Error writing"); + msg_perr("Error writing"); return 1; } } @@ -687,14 +678,14 @@ spi_disable_blockprotect(); /* Erase first */ - printf("Erasing flash before programming... "); + msg_pinfo("Erasing flash before programming... "); if (erase_flash(flash)) { - fprintf(stderr, "ERASE FAILED!\n"); + msg_perr("ERASE FAILED!\n"); return -1; } - printf("done.\n"); + msg_pinfo("done.\n"); - printf("Programming page: \n"); + msg_pinfo("Programming page: \n"); for (i = 0; i < total_size / erase_size; i++) { if (spi_controller == SPI_CONTROLLER_VIA) maxdata = 16; @@ -706,7 +697,7 @@ } } - printf("\n"); + msg_pinfo("\n"); return rc; } @@ -728,7 +719,7 @@ /* FIXME: Reprogram opcodes if possible. Autodetect type of * opcode by checking readcnt/writecnt. */ - printf_debug("Invalid OPCODE 0x%02x\n", cmd); + msg_pdbg("Invalid OPCODE 0x%02x\n", cmd); return SPI_INVALID_OPCODE; } @@ -743,21 +734,21 @@ */ if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) && (writecnt != 4)) { - fprintf(stderr, "%s: Internal command size error for opcode " + msg_perr("%s: Internal command size error for opcode " "0x%02x, got writecnt=%i, want =4\n", __func__, cmd, writecnt); return SPI_INVALID_LENGTH; } if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) && (writecnt != 1)) { - fprintf(stderr, "%s: Internal command size error for opcode " + msg_perr("%s: Internal command size error for opcode " "0x%02x, got writecnt=%i, want =1\n", __func__, cmd, writecnt); return SPI_INVALID_LENGTH; } if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) && (writecnt < 4)) { - fprintf(stderr, "%s: Internal command size error for opcode " + msg_perr("%s: Internal command size error for opcode " "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd, writecnt); return SPI_INVALID_LENGTH; @@ -765,7 +756,7 @@ if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) && (readcnt)) { - fprintf(stderr, "%s: Internal command size error for opcode " + msg_perr("%s: Internal command size error for opcode " "0x%02x, got readcnt=%i, want =0\n", __func__, cmd, readcnt); return SPI_INVALID_LENGTH; @@ -792,7 +783,7 @@ result = run_opcode(*opcode, addr, count, data); if (result) { - printf_debug("run OPCODE 0x%02x failed\n", opcode->opcode); + msg_pdbg("run OPCODE 0x%02x failed\n", opcode->opcode); } return result; @@ -817,7 +808,7 @@ */ if (find_preop(curopcodes, (cmds + 1)->writearr[0]) != -1) { - fprintf(stderr, "%s: Two subsequent " + msg_perr("%s: Two subsequent " "preopcodes 0x%02x and 0x%02x, " "ignoring the first.\n", __func__, cmds->writearr[0], @@ -829,7 +820,7 @@ * No need to bother with fixups. */ if (!ichspi_lock) { - printf_debug("%s: FIXME: Add on-the-fly" + msg_pdbg("%s: FIXME: Add on-the-fly" " reprogramming of the " "chipset opcode list.\n", __func__); Modified: trunk/pcidev.c ============================================================================== --- trunk/pcidev.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/pcidev.c Fri May 7 22:09:04 2010 (r997) @@ -45,7 +45,7 @@ */ addr = pci_read_long(dev, bar); - printf("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", + msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", devs[i].vendor_name, devs[i].device_name, dev->vendor_id, dev->device_id, dev->bus, dev->dev, dev->func); @@ -66,7 +66,7 @@ } if (devs[i].status == NT) { - printf("===\nThis PCI device is UNTESTED. Please " + msg_pinfo("===\nThis PCI device is UNTESTED. Please " "report the 'flashrom -p xxxx' output \n" "to flashrom(a)flashrom.org if it works " "for you. Thank you for your help!\n===\n"); @@ -95,7 +95,7 @@ filter.vendor = vendor_id; if (pcidev_bdf != NULL) { if ((msg = pci_filter_parse_slot(&filter, pcidev_bdf))) { - fprintf(stderr, "Error: %s\n", msg); + msg_perr("Error: %s\n", msg); exit(1); } } @@ -112,10 +112,10 @@ /* Only continue if exactly one supported PCI dev has been found. */ if (found == 0) { - fprintf(stderr, "Error: No supported PCI device found.\n"); + msg_perr("Error: No supported PCI device found.\n"); exit(1); } else if (found > 1) { - fprintf(stderr, "Error: Multiple supported PCI devices found. " + msg_perr("Error: Multiple supported PCI devices found. " "Use 'flashrom -p xxxx:bb:dd.f' \n" "to explicitly select the card with the given BDF " "(PCI bus, device, function).\n"); @@ -130,7 +130,7 @@ int i; for (i = 0; devs[i].vendor_name != NULL; i++) { - printf("%s %s [%02x:%02x]%s\n", devs[i].vendor_name, + msg_pinfo("%s %s [%02x:%02x]%s\n", devs[i].vendor_name, devs[i].device_name, devs[i].vendor_id, devs[i].device_id, (devs[i].status == NT) ? " (untested)" : ""); Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/physmap.c Fri May 7 22:09:04 2010 (r997) @@ -158,7 +158,7 @@ if (-1 == fd_mem_cached) { /* Open the memory device CACHED. */ if (-1 == (fd_mem_cached = open(MEM_DEV, O_RDWR))) { - perror("Critical error: open(" MEM_DEV ")"); + msg_perr("Critical error: open(" MEM_DEV "): %s", strerror(errno)); exit(2); } } @@ -171,7 +171,7 @@ void physunmap(void *virt_addr, size_t len) { if (len == 0) { - printf_debug("Not unmapping zero size at %p\n", virt_addr); + msg_pspew("Not unmapping zero size at %p\n", virt_addr); return; } @@ -189,18 +189,18 @@ void *virt_addr; if (len == 0) { - printf_debug("Not mapping %s, zero size at 0x%08lx.\n", + msg_pspew("Not mapping %s, zero size at 0x%08lx.\n", descr, phys_addr); return NULL; } if ((getpagesize() - 1) & len) { - fprintf(stderr, "Mapping %s at 0x%08lx, unaligned size 0x%lx.\n", + msg_perr("Mapping %s at 0x%08lx, unaligned size 0x%lx.\n", descr, phys_addr, (unsigned long)len); } if ((getpagesize() - 1) & phys_addr) { - fprintf(stderr, "Mapping %s, 0x%lx bytes at unaligned 0x%08lx.\n", + msg_perr("Mapping %s, 0x%lx bytes at unaligned 0x%08lx.\n", descr, (unsigned long)len, phys_addr); } @@ -213,15 +213,17 @@ if (NULL == virt_addr) { if (NULL == descr) descr = "memory"; - fprintf(stderr, "Error accessing %s, 0x%lx bytes at 0x%08lx\n", descr, (unsigned long)len, phys_addr); + msg_perr("Error accessing %s, 0x%lx bytes at 0x%08lx\n", descr, (unsigned long)len, phys_addr); perror(MEM_DEV " mmap failed"); +#ifdef __linux__ if (EINVAL == errno) { - fprintf(stderr, "In Linux this error can be caused by the CONFIG_NONPROMISC_DEVMEM (<2.6.27),\n"); - fprintf(stderr, "CONFIG_STRICT_DEVMEM (>=2.6.27) and CONFIG_X86_PAT kernel options.\n"); - fprintf(stderr, "Please check if either is enabled in your kernel before reporting a failure.\n"); - fprintf(stderr, "You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); - fprintf(stderr, "disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); + msg_perr("In Linux this error can be caused by the CONFIG_NONPROMISC_DEVMEM (<2.6.27),\n"); + msg_perr("CONFIG_STRICT_DEVMEM (>=2.6.27) and CONFIG_X86_PAT kernel options.\n"); + msg_perr("Please check if either is enabled in your kernel before reporting a failure.\n"); + msg_perr("You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); + msg_perr("disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); } +#endif if (!mayfail) exit(3); } @@ -306,7 +308,7 @@ sprintf(msrfilename, "/dev/cpu/%d/msr", cpu); if (fd_msr != -1) { - printf("MSR was already initialized\n"); + msg_pinfo("MSR was already initialized\n"); return -1; } @@ -314,7 +316,7 @@ if (fd_msr < 0) { perror("Error while opening /dev/cpu/0/msr"); - printf("Did you run 'modprobe msr'?\n"); + msg_pinfo("Did you run 'modprobe msr'?\n"); return -1; } @@ -324,7 +326,7 @@ void cleanup_cpu_msr(void) { if (fd_msr == -1) { - printf("No MSR initialized.\n"); + msg_pinfo("No MSR initialized.\n"); return; } @@ -389,7 +391,7 @@ sprintf(msrfilename, "/dev/cpu%d", cpu); if (fd_msr != -1) { - printf("MSR was already initialized\n"); + msg_pinfo("MSR was already initialized\n"); return -1; } @@ -397,7 +399,7 @@ if (fd_msr < 0) { perror("Error while opening /dev/cpu0"); - printf("Did you install ports/sysutils/devcpu?\n"); + msg_pinfo("Did you install ports/sysutils/devcpu?\n"); return -1; } @@ -407,7 +409,7 @@ void cleanup_cpu_msr(void) { if (fd_msr == -1) { - printf("No MSR initialized.\n"); + msg_pinfo("No MSR initialized.\n"); return; } @@ -445,7 +447,7 @@ int setup_cpu_msr(int cpu) { - printf("No MSR support for your OS yet.\n"); + msg_pinfo("No MSR support for your OS yet.\n"); return -1; } Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Wed Apr 28 17:22:14 2010 (r996) +++ trunk/spi.c Fri May 7 22:09:04 2010 (r997) @@ -130,7 +130,7 @@ const unsigned char *writearr, unsigned char *readarr) { if (!spi_programmer[spi_controller].command) { - fprintf(stderr, "%s called, but SPI is unsupported on this " + msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug.\n", __func__); return 1; } @@ -142,7 +142,7 @@ int spi_send_multicommand(struct spi_command *cmds) { if (!spi_programmer[spi_controller].multicommand) { - fprintf(stderr, "%s called, but SPI is unsupported on this " + msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug.\n", __func__); return 1; } @@ -182,7 +182,7 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { if (!spi_programmer[spi_controller].read) { - fprintf(stderr, "%s called, but SPI read is unsupported on this" + msg_perr("%s called, but SPI read is unsupported on this" " hardware. Please report a bug.\n", __func__); return 1; } @@ -197,7 +197,7 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) { if (!spi_programmer[spi_controller].write_256) { - fprintf(stderr, "%s called, but SPI page write is unsupported " + msg_perr("%s called, but SPI page write is unsupported " " on this hardware. Please report a bug.\n", __func__); return 1; }

1 0

(no subject)
by Steve Herber 06 May '10

06 May '10

Hello: I ran flashrom on an asus P4P800-VM motherboard and got this error: tux tmp # flashrom -w P4PVM1018.rom flashrom v0.9.1-r710 No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x00007810! Expected=0xff, Read=0x3c, failed byte count from 0x00000000-0x0000ffff: 0x8732 ERASE FAILED! ERASE FAILED! ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF! Any suggestions? Thanks, -- Steve Herber herber(a)thing.com work: 206-221-7262 Software Engineer, UW Medicine, IT Services home: 425-454-2399

3 3

ERASE works on with a Macronix MX25L8005 (ASUS M3A-H/HDMI)
by Emil Gruno 05 May '10

05 May '10

flashrom v0.9.1-r946 No coreboot table found. Found ITE Super I/O, id 8716 Found chipset "AMD SB700/SB710/SB750", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: ERASE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash before programming... Erasing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff, 0x001000-0x001fff, 0x002000-0x002fff, 0x003000-0x003fff, 0x004000-0x004fff, 0x005000-0x005fff, 0x006000-0x006fff, 0x007000-0x007fff, 0x008000-0x008fff, 0x009000-0x009fff, 0x00a000-0x00afff, 0x00b000-0x00bfff, 0x00c000-0x00cfff, 0x00d000-0x00dfff, 0x00e000-0x00efff, 0x00f000-0x00ffff, 0x010000-0x010fff, 0x011000-0x011fff, 0x012000-0x012fff, 0x013000-0x013fff, 0x014000-0x014fff, 0x015000-0x015fff, 0x016000-0x016fff, 0x017000-0x017fff, 0x018000-0x018fff, 0x019000-0x019fff, 0x01a000-0x01afff, 0x01b000-0x01bfff, 0x01c000-0x01cfff, 0x01d000-0x01dfff, 0x01e000-0x01efff, 0x01f000-0x01ffff, 0x020000-0x020fff, 0x021000-0x021fff, 0x022000-0x022fff, 0x023000-0x023fff, 0x024000-0x024fff, 0x025000-0x025fff, 0x026000-0x026fff, 0x027000-0x027fff, 0x028000-0x028fff, 0x029000-0x029fff, 0x02a000-0x02afff, 0x02b000-0x02bfff, 0x02c000-0x02cfff, 0x02d000-0x02dfff, 0x02e000-0x02efff, 0x02f000-0x02ffff, 0x030000-0x030fff, 0x031000-0x031fff, 0x032000-0x032fff, 0x033000-0x033fff, 0x034000-0x034fff, 0x035000-0x035fff, 0x036000-0x036fff, 0x037000-0x037fff, 0x038000-0x038fff, 0x039000-0x039fff, 0x03a000-0x03afff, 0x03b000-0x03bfff, 0x03c000-0x03cfff, 0x03d000-0x03dfff, 0x03e000-0x03efff, 0x03f000-0x03ffff, 0x040000-0x040fff, 0x041000-0x041fff, 0x042000-0x042fff, 0x043000-0x043fff, 0x044000-0x044fff, 0x045000-0x045fff, 0x046000-0x046fff, 0x047000-0x047fff, 0x048000-0x048fff, 0x049000-0x049fff, 0x04a000-0x04afff, 0x04b000-0x04bfff, 0x04c000-0x04cfff, 0x04d000-0x04dfff, 0x04e000-0x04efff, 0x04f000-0x04ffff, 0x050000-0x050fff, 0x051000-0x051fff, 0x052000-0x052fff, 0x053000-0x053fff, 0x054000-0x054fff, 0x055000-0x055fff, 0x056000-0x056fff, 0x057000-0x057fff, 0x058000-0x058fff, 0x059000-0x059fff, 0x05a000-0x05afff, 0x05b000-0x05bfff, 0x05c000-0x05cfff, 0x05d000-0x05dfff, 0x05e000-0x05efff, 0x05f000-0x05ffff, 0x060000-0x060fff, 0x061000-0x061fff, 0x062000-0x062fff, 0x063000-0x063fff, 0x064000-0x064fff, 0x065000-0x065fff, 0x066000-0x066fff, 0x067000-0x067fff, 0x068000-0x068fff, 0x069000-0x069fff, 0x06a000-0x06afff, 0x06b000-0x06bfff, 0x06c000-0x06cfff, 0x06d000-0x06dfff, 0x06e000-0x06efff, 0x06f000-0x06ffff, 0x070000-0x070fff, 0x071000-0x071fff, 0x072000-0x072fff, 0x073000-0x073fff, 0x074000-0x074fff, 0x075000-0x075fff, 0x076000-0x076fff, 0x077000-0x077fff, 0x078000-0x078fff, 0x079000-0x079fff, 0x07a000-0x07afff, 0x07b000-0x07bfff, 0x07c000-0x07cfff, 0x07d000-0x07dfff, 0x07e000-0x07efff, 0x07f000-0x07ffff, 0x080000-0x080fff, 0x081000-0x081fff, 0x082000-0x082fff, 0x083000-0x083fff, 0x084000-0x084fff, 0x085000-0x085fff, 0x086000-0x086fff, 0x087000-0x087fff, 0x088000-0x088fff, 0x089000-0x089fff, 0x08a000-0x08afff, 0x08b000-0x08bfff, 0x08c000-0x08cfff, 0x08d000-0x08dfff, 0x08e000-0x08efff, 0x08f000-0x08ffff, 0x090000-0x090fff, 0x091000-0x091fff, 0x092000-0x092fff, 0x093000-0x093fff, 0x094000-0x094fff, 0x095000-0x095fff, 0x096000-0x096fff, 0x097000-0x097fff, 0x098000-0x098fff, 0x099000-0x099fff, 0x09a000-0x09afff, 0x09b000-0x09bfff, 0x09c000-0x09cfff, 0x09d000-0x09dfff, 0x09e000-0x09efff, 0x09f000-0x09ffff, 0x0a0000-0x0a0fff, 0x0a1000-0x0a1fff, 0x0a2000-0x0a2fff, 0x0a3000-0x0a3fff, 0x0a4000-0x0a4fff, 0x0a5000-0x0a5fff, 0x0a6000-0x0a6fff, 0x0a7000-0x0a7fff, 0x0a8000-0x0a8fff, 0x0a9000-0x0a9fff, 0x0aa000-0x0aafff, 0x0ab000-0x0abfff, 0x0ac000-0x0acfff, 0x0ad000-0x0adfff, 0x0ae000-0x0aefff, 0x0af000-0x0affff, 0x0b0000-0x0b0fff, 0x0b1000-0x0b1fff, 0x0b2000-0x0b2fff, 0x0b3000-0x0b3fff, 0x0b4000-0x0b4fff, 0x0b5000-0x0b5fff, 0x0b6000-0x0b6fff, 0x0b7000-0x0b7fff, 0x0b8000-0x0b8fff, 0x0b9000-0x0b9fff, 0x0ba000-0x0bafff, 0x0bb000-0x0bbfff, 0x0bc000-0x0bcfff, 0x0bd000-0x0bdfff, 0x0be000-0x0befff, 0x0bf000-0x0bffff, 0x0c0000-0x0c0fff, 0x0c1000-0x0c1fff, 0x0c2000-0x0c2fff, 0x0c3000-0x0c3fff, 0x0c4000-0x0c4fff, 0x0c5000-0x0c5fff, 0x0c6000-0x0c6fff, 0x0c7000-0x0c7fff, 0x0c8000-0x0c8fff, 0x0c9000-0x0c9fff, 0x0ca000-0x0cafff, 0x0cb000-0x0cbfff, 0x0cc000-0x0ccfff, 0x0cd000-0x0cdfff, 0x0ce000-0x0cefff, 0x0cf000-0x0cffff, 0x0d0000-0x0d0fff, 0x0d1000-0x0d1fff, 0x0d2000-0x0d2fff, 0x0d3000-0x0d3fff, 0x0d4000-0x0d4fff, 0x0d5000-0x0d5fff, 0x0d6000-0x0d6fff, 0x0d7000-0x0d7fff, 0x0d8000-0x0d8fff, 0x0d9000-0x0d9fff, 0x0da000-0x0dafff, 0x0db000-0x0dbfff, 0x0dc000-0x0dcfff, 0x0dd000-0x0ddfff, 0x0de000-0x0defff, 0x0df000-0x0dffff, 0x0e0000-0x0e0fff, 0x0e1000-0x0e1fff, 0x0e2000-0x0e2fff, 0x0e3000-0x0e3fff, 0x0e4000-0x0e4fff, 0x0e5000-0x0e5fff, 0x0e6000-0x0e6fff, 0x0e7000-0x0e7fff, 0x0e8000-0x0e8fff, 0x0e9000-0x0e9fff, 0x0ea000-0x0eafff, 0x0eb000-0x0ebfff, 0x0ec000-0x0ecfff, 0x0ed000-0x0edfff, 0x0ee000-0x0eefff, 0x0ef000-0x0effff, 0x0f0000-0x0f0fff, 0x0f1000-0x0f1fff, 0x0f2000-0x0f2fff, 0x0f3000-0x0f3fff, 0x0f4000-0x0f4fff, 0x0f5000-0x0f5fff, 0x0f6000-0x0f6fff, 0x0f7000-0x0f7fff, 0x0f8000-0x0f8fff, 0x0f9000-0x0f9fff, 0x0fa000-0x0fafff, 0x0fb000-0x0fbfff, 0x0fc000-0x0fcfff, 0x0fd000-0x0fdfff, 0x0fe000-0x0fefff, 0x0ff000-0x0fffff, SUCCESS. done. Programming flash done. COMPLETE. Verifying flash... VERIFIED. BR, Emil Gruno

1 0

SREC Files
by KC2WNG 04 May '10

04 May '10

Hi Guys I Was wondering if you guys have ever worked on editing SREC files, and figuring out the checksum mechanism

2 1

flashrom external programming with different usb high speed converter
by Matthias Olescher 04 May '10

04 May '10

Hello, as I can see are you using one port of an FT2232H for the SPI programming. Unfortunatly for germans, the chip and the converter board is only aviable from Digikey. Is it also possible to only use full speed with FT232 or even low Speed and V-USB? If high speed is necessary, can the program be changed that it works with http://www-user.tu-chemnitz.de/~heha/bastelecke/Rund%20um%20den%20PC/USB2LP… ? Thank you in advance. Matthias -- Das war's. Werbung bitte nicht beachten: GRATIS für alle GMX-Mitglieder: Die maxdome Movie-FLAT! Jetzt freischalten unter http://portal.gmx.net/de/go/maxdome01

2 1

on chip status table
by FENG Yu Ning 02 May '10

02 May '10

A successful flash chip operation is closely related to a few factors other than the flash chip - southbridge, embedded controller, special enabling operation of a particular board and the flashrom revision. Shall we include other related information in the chip status table? Let us put aside how to store the table first.

1 0

How do you calculate CRC/Checksum for Intel ICH8M-E ?
by Bill Flanders (wtflanders) 01 May '10

01 May '10

Hi, Any idea of what algorithm and bytes to use to update the CRC/Checksum in the flash image? The mac address is stored in the image. I have written a script to update the mac address and know where the CRC/Checksum is. I have tried various algorithms (those supported by Hex Workshop- Checksum-8 and -16, CRC-8 and -16, etc. w/1's and 2's complements) but am unable to duplicate a known checksum. Hardware is a Kontron ETX Express module, flashrom reports: 'Found Chipset "Intel ICH8M-E" ...', 'Found chip "SST SST25VF016B" ...' Thanks in advance, Bill Flanders

2 1

Re: [flashrom] Flashrom - DOS version report
by Carl-Daniel Hailfinger 01 May '10

01 May '10

Hi, [fullquote for flashrom(a)flashrom.org] On 23.03.2010 22:58, RayeR wrote: > >That is very strange. Do you have a log? > >SB600 should work fine. Maybe the SPI chip is not > >attached to the SB600 but instead to the SuperI/O. > >Can you try > >flashrom -p it87spi > > Yes here's it: > > C:\F>flashrom.exe -p it87spi > flashrom v0.9.1-r933 > Error: Programmer initialization failed. OK, so it is not ITE IT87. > C:\F>flashrom.exe -V -r > flashrom v0.9.1-r933 > No coreboot table found. > DMI string system-manufacturer: "Dell Inc. " > DMI string system-product-name: "OptiPlex 320 " > DMI string system-version: "Not Specified" > DMI string baseboard-manufacturer: "Dell Inc. " > DMI string baseboard-product-name: "0CU395" > DMI string baseboard-version: " " > DMI string chassis-type: "Tower" > Found chipset "AMD SB600", enabling flash write... SPI base address is > at 0xd8000 > Error accessing SB600 SPI registers, 0x1000 bytes at 0x000d8000 > dpmi mmap failed: No such file or directory (ENOENT) Ah yes. That's a limitation of the DOS port of flashrom. Usually the SB600 SPI base address is near the top of the address space (4 GB). On your board it is below 1 MB, and AFAIK Rudolf said that we can't map any region below 1 MB as uncached due to CWSDPMI/DJGPP limitations. If anyone has an idea how to overcome these limitations, we can fix flashrom for this special case. > See PCI device listing attached. > > >The W25x40 supports multiple erase commands, > >and your chipset does not allow flashrom to use > >the spi_block_erase_20 command. Flashrom notices > >that this command failed and tries another erase command which works. > > OK > > >Yes, strange. Maybe that happens as side effect from DJGPP compilation? > > I don't know... > > >It should try only 2 times. If it tries more often, > >we have to check the code (bug?). I think Rudolf(?) said that there > >are problems if we try to run a CWSDPMI app (dmidecode) from another > >CWSDPMI app (flashrom). > >Does it work if dmidecode.exe is in the PATH? > >Hm. DMIDECODE.EXE is a name with 9+3 letters. That can't work on old > DOS. > > Yes it works with dmidecode in path but nobody told me that I need it. > On my home PC I already have dmidecode for DOS in my utilities > directory. The file name is not problem because of DJGPP is smart > and do some file name translation. If there's no LFN support it > tries to look for "dmidecod.exe" and when run on LFN enabled OS > it will use "dmidecode.exe". But it's different LFN truncating > mode than windows use ("dmidec~1.exe"). I don't know why but e.g. > DJGPP PKUNZIP tool use filename truncate this way without ~. > But it would be better to check if both version of name exist and > display non-confusing error message when nothing found. Michael? Is there a good way to handle this? Regards, Carl-Daniel -- http://www.hailfinger.org/

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flashrom May 2010