flashrom August 2009

flashrom@flashrom.org

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124 discussions

[PATCH] Add ICH9 Engineering sample to chipset enables
by Carl-Daniel Hailfinger 21 Aug '09

21 Aug '09

Anne Le Coq <annyvonne.le_coq(a)alcatel-lucent.fr> reported that flashrom didn't recognize her ICH9 LPC controller. According to http://pci-ids.ucw.cz/read/PC/8086/2910 the ID 0x8086/0x2910 was only used for an engineering sample. No intel doc mentions this ID at all. Anne, could you reply to this mail with "lspci -nnvvvxxx" as attachment? Thanks! This list accepts attachments. If the patch below is what you had in mind and detecting the chipset works for you, please reply with Acked-by: Anne Le Coq <annyvonne.le_coq(a)alcatel-lucent.fr> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> This patch will also appear at the top of http://patchwork.coreboot.org/project/flashrom/list/ so if you have trouble extracting the patch from this mail, you can download it from there. Index: flashrom-ich9_engineeringsample/chipset_enable.c =================================================================== --- flashrom-ich9_engineeringsample/chipset_enable.c (Revision 695) +++ flashrom-ich9_engineeringsample/chipset_enable.c (Arbeitskopie) @@ -1012,6 +1012,7 @@ {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9}, {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9}, {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9}, + {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9}, {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH] Add ICH9 Engineering sample to chipset enables
by Carl-Daniel Hailfinger 21 Aug '09

21 Aug '09

bouncing this mail... On 21.08.2009 18:41, LE COQ ANNYVONNE wrote: > Acked-by: Anne Le Coq <annyvonne.le_coq(a)alcatel-lucent.fr> > > Hi Carl-Daniel, > > It's the modification I've done to accept the ICH9, and it works fine. I just mention "ICH9" instead of "ICH9 Engineering Sample", but I don't think it's very important. > > My problem now is that the opcode 06 is unknown in the opcode table. > To continue my test, I replace one of unused opcode (0B9H) by 06 and it's better. But it's not a good solution... > Then, after that, I can only read, write and erase my flash till A000H. > I think it's because I use the ICH9 in descriptor mode. > I have the following fault: > ERROR at 0x0000a000: Expected=0xff, Read=0x00 > Have you got an idea about this issue ? > Thanks > Anne >

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Re: [flashrom] [PATCH] Add ICH9 Engineering sample to chipset enables
by Carl-Daniel Hailfinger 21 Aug '09

21 Aug '09

bouncing this mail... On 21.08.2009 18:55, LE COQ ANNYVONNE wrote: > Hello, > I have to leave my office now. I'll send the lspci result on Monday. > I'm working on an INTEL demo board called GreenCity: > 2 Nehalem processors, ICH9 + Tylersburg. > The problem is that I'm not able to flash a new BIOS ... > > I'm OK with the patch below, I've tested it on the GreenCity MotherBoard > Have a good week end > Anne > -- http://www.hailfinger.org/

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[commit] r696 - trunk
by svn＠flashrom.org 21 Aug '09

21 Aug '09

Author: hailfinger Date: 2009-08-21 19:26:13 +0200 (Fri, 21 Aug 2009) New Revision: 696 Modified: trunk/chipset_enable.c Log: Anne Le Coq <annyvonne.le_coq(a)alcatel-lucent.fr> reported that flashrom didn't recognize her ICH9 LPC controller on the Green City Intel Customer Reference Board with ICH9 + Tylersburg Chipset. According to http://pci-ids.ucw.cz/read/PC/8086/2910 the ID 0x8086/0x2910 was used for engineering samples. No intel doc mentions this ID at all. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Anne Le Coq <annyvonne.le_coq(a)alcatel-lucent.fr> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-08-20 18:45:18 UTC (rev 695) +++ trunk/chipset_enable.c 2009-08-21 17:26:13 UTC (rev 696) @@ -1012,6 +1012,7 @@ {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9}, {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9}, {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9}, + {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9}, {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},

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Re: [flashrom] [PATCH] Add ICH9 Engineering sample to chipset enables
by Carl-Daniel Hailfinger 21 Aug '09

21 Aug '09

forwarding to list... -------- Original Message -------- Subject: RE: [flashrom] [PATCH] Add ICH9 Engineering sample to chipset enables Date: Fri, 21 Aug 2009 18:41:36 +0200 From: LE COQ ANNYVONNE <Annyvonne.Le_Coq(a)alcatel-lucent.fr> To: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> References: <4A8EB02D.9000607(a)gmx.net> Acked-by: Anne Le Coq <annyvonne.le_coq(a)alcatel-lucent.fr> Hi Carl-Daniel, It's the modification I've done to accept the ICH9, and it works fine. I just mention "ICH9" instead of "ICH9 Engineering Sample", but I don't think it's very important. My problem now is that the opcode 06 is unknown in the opcode table. To continue my test, I replace one of unused opcode (0B9H) by 06 and it's better. But it's not a good solution... Then, after that, I can only read, write and erase my flash till A000H. I think it's because I use the ICH9 in descriptor mode. I have the following fault: ERROR at 0x0000a000: Expected=0xff, Read=0x00 Have you got an idea about this issue ? Thanks Anne

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bad flash ?
by Benjamin BELLEC 21 Aug '09

21 Aug '09

Hello, I have tried to flash the BIOS of my motherboard. It's a Gigabyte G33M-DS2R (ICH9R + SST SST25VF080B" (1024 KB)). [root@scarabee benjamin]# flashrom --version flashrom v0.9.0 (on Fedora 11 x86_64) Here is the log of the flash (my motherboard was previously in version F7) : flashrom --write ./G33MDS2R.F8 Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... OK. Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Programming page: [root@scarabee motherboard_bios_ga-g33m-ds2r_f8]# and I check the BIOS : [root@scarabee motherboard_bios_ga-g33m-ds2r_f8]# flashrom --verify ./G33MDS2R.F8 Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... OK. Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... FAILED at 0x00000000! Expected=0x00, Read=0x01 [root@scarabee motherboard_bios_ga-g33m-ds2r_f8]# and when I try to erase it : [root@scarabee benjamin]# flashrom --erase Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... OK. Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Erasing flash chip... FAILED! ERROR at 0x00000000: Expected=0xff, Read=0x01 [root@scarabee benjamin]# I can post the entire log (--write --verbose) if you want. What can I do, is my BIOS really write or not ? Can I reboot ? Thanks for your time. Benjamin (from France)

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Non-working board submission: Matsonic MS8308E
by Putlinuxonit 21 Aug '09

21 Aug '09

Hi, I've tested this board with flashrom-0.9.0-r695 as well as superiotool r4424. Also contained are dumps from* #lspci -vvnnxxxx*, *#dmidecode* and *#lshw*. As always, a lot of the info is probably duplicated but is provided for the sake of completeness. I'm available for further testing if required. Bios: AMI > Board: Matsonic MS8308E http://www.motherboard.cz/mb/matsonic/MS8308E.htm > Flash Chip: W49F002UP12B (PLCC) > Chipset: Sis 730 > Enjoy!, Udu E. Ogah .~~~~~~~~~~.

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#3: OSError: (13, 'Permission denied')
by flashrom 21 Aug '09

21 Aug '09

#3: OSError: (13, 'Permission denied') ---------------------------------+------------------------------------------ Reporter: hailfinger | Owner: hailfinger Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ ==== How to Reproduce ==== While doing a POST operation on `/attachment/ticket/2`, Trac issued an internal error. ''(please provide additional details here)'' Request parameters: {{{ {'__FORM_TOKEN': u'88590e6c536c68a9192d038f', 'action': u'new', 'attachment': FieldStorage('attachment', 'test.c', '#include <stdio.h>\n#include <stdint.h>\n\nvoid u64function(uint64_t bar)\n{\n\tprintf("%llx\\n", bar);\n}\n\nint main()\n{\n\tuint32_t hi = 0xdeadbeef;\n\tuint32_t lo = 0xcafebabe;\n\tu64function((((uint64_t) hi) << 32) | lo);\n\treturn 0;\n}\n'), 'description': u'test attachment', 'id': u'2', 'path': u'2', 'realm': u'ticket'} }}} User Agent was: `Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.8.1.19) Gecko/20081213 SUSE/1.1.14-1.1 SeaMonkey/1.1.14` ==== System Information ==== || '''Trac''' || `0.11.5` || || '''Python''' || `2.6 (r26:66714, Feb 3 2009, 20:49:49) ` [[br]] `[GCC 4.3.2 [gcc-4_3-branch revision 141291]]` || || '''setuptools''' || `0.6c9` || || '''SQLite''' || `3.6.4` || || '''pysqlite''' || `2.4.1` || || '''Genshi''' || `0.5.1` || || '''Pygments''' || `1.0` || || '''Subversion''' || `1.6.4 (r38063)` || || '''jQuery:''' || `1.2.6` || ==== Python Traceback ==== {{{ Traceback (most recent call last): File "/usr/lib64/python2.6/site-packages/trac/web/main.py", line 444, in _dispatch_request dispatcher.dispatch(req) File "/usr/lib64/python2.6/site-packages/trac/web/main.py", line 205, in dispatch resp = chosen_handler.process_request(req) File "/usr/lib64/python2.6/site-packages/trac/attachment.py", line 398, in process_request self._do_save(req, attachment) File "/usr/lib64/python2.6/site-packages/trac/attachment.py", line 612, in _do_save attachment.insert(filename, upload.file, size) File "/usr/lib64/python2.6/site-packages/trac/attachment.py", line 219, in insert os.makedirs(self.path) File "/usr/lib64/python2.6/os.py", line 150, in makedirs makedirs(head, mode) File "/usr/lib64/python2.6/os.py", line 157, in makedirs mkdir(name, mode) OSError: [Errno 13] Permission denied: '/srv/trac/flashrom/attachments/ticket' }}} -- Ticket URL: <http://www.flashrom.org/trac/flashrom/ticket/3> flashrom <http://www.flashrom.org/>

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#2: test attachments
by flashrom 21 Aug '09

21 Aug '09

#2: test attachments ---------------------------------+------------------------------------------ Reporter: hailfinger | Owner: hailfinger Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ It seems that attachments do not work... -- Ticket URL: <http://www.flashrom.org/trac/flashrom/ticket/2> flashrom <http://www.flashrom.org/>

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flashrom support for intel pro100 - worthwhile?
by Marko Kraljevic 20 Aug '09

20 Aug '09

The support for 3com NICs got me thinking about other NICs with boot ROMs. I've got a few intel 100 pro PCI cards around, with the 82558 chipset. They have a PLCC socket, and a parallel interface; so they *should* support any PLCC 28/29 family chips. There's good documentation available, so I think adding support should not be too difficult. The only problem is, 82558 only supports up to 64kB [A0:16], and 82559 only supports up to 128kB [A0:17]. So I'm not sure if I should bother, especially with the PLCC socket, and the fact that we already have support for the cheap and common 3com cards. If you guys think it would be worthwhile to support, I can take a stab at it though. :-) datasheet for 82558: http://developer.intel.com/design/network/datashts/29736001.pdf datasheet for 82559: http://download.intel.com/design/network/datashts/73825902.pdf I'll take a look into some of intel's other ethernet controller chips, see if anything supports > 1Mbit. Although I have a suspicion that more modern controllers probably moved away from the parallel bus and/or dumped boot rom altogether. And of course - I'll have to make sure someone sold a physical card with them and a ROM socket! Mark

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flashrom August 2009