Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/84595?usp=email )
Change subject: ichspi: const-correct POSSIBLE_OPCODES[] ......................................................................
ichspi: const-correct POSSIBLE_OPCODES[]
POSSIBLE_OPCODES[] is never modified, so mark it as read-only.
Change-Id: I217f8a9e50b9e2e9f2731adec89a46780874c754 Signed-off-by: persmule persmule@hardenedlinux.org Reviewed-on: https://review.coreboot.org/c/flashrom/+/84595 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Anastasia Klimchuk aklm@chromium.org Reviewed-by: Nikolai Artemiev nartemiev@google.com --- M ichspi.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: Nikolai Artemiev: Looks good to me, approved build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved
diff --git a/ichspi.c b/ichspi.c index 358d9f4..d53e671 100644 --- a/ichspi.c +++ b/ichspi.c @@ -399,7 +399,7 @@ * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode * is needed which is currently not in the chipset OPCODE table */ -static OPCODE POSSIBLE_OPCODES[] = { +static const OPCODE POSSIBLE_OPCODES[] = { {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector