Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40325 )
Change subject: Add writeprotect support infrastructure ......................................................................
Patch Set 12:
(1 comment)
Patchset:
PS12:
Did somebody look into Hatim's patches [1]? I didn't but feel like […]
The slow down here is because the cros implementation (which I agree is very poor) is being rewritten to line more up with the patches pointed out on the mailing list to come up with something to keep moving forwards with. I believe that was the desire of the community given the above so that is what I am working towards.
UPDATE: The immediate thing at the moment that is happening in our tree is to remove the `.wp` field out of flashchip struct and replace it with a lookup table in writeprotect.c this is to make writeprotect more self-contained. Also, the other part is is breaking it up a little just as Angel pointed out but we have to unroll a few problems before that with ichspi.
BACKGROUND: I don't think anything is actually stuck here just hard to resource as there isn't really a team of people working on it, just me trying to pull the show together largely on my own. I am working on mentoring others to help grow the participation however that takes its own time and effort to. These are things beyond my control so I can only do my personal best to focus efforts and bring attention to help things move forwards.
ISSUES: Some other background things add time to this such as https://review.coreboot.org/c/flashrom/+/45748 which is a bit of a mess due to the non-standardness of these opcodes. I have been trying to talk to some of these companies and get them onboard to helping chip-level support in Flashrom directly to some success, https://github.com/flashrom/flashrom/commit/32f4cb4ffa2854354f00e5facc9ccb8c... its all just super hard to bring so many things together on my own and this is fundamentally the limiting factor.
REASONING: As for the writeprotect support I have to figure out how to modify it to gel more into upstream piece by piece while maintaining support for all the shipped hardware without breaking it. The current code has zero tests apart from the AVL tooling which only gets run once for when the chip is first qualified. The framework at least allows the chip AVL qualification tool to be run using the upstream Flashrom so we can have XMC or similar working directly here and not in our tree.
Hope this helps shed some light and thanks for keeping a eye on this as well!