[flashrom-gerrit] [M] Change in flashrom[master]: flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E

[Anastasia Klimchuk (Code Review)]

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/66215 )

(

9 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E
......................................................................

flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E

Change-Id: Ib0f3cb9516cea7bb678842a358a82099221e1ed9
Signed-off-by: Sergii Dmytruk 
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66215
Reviewed-by: Anastasia Klimchuk 
Tested-by: build bot (Jenkins) 
---
M flashchips.c
1 file changed, 64 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Anastasia Klimchuk: Looks good to me, approved

diff --git a/flashchips.c b/flashchips.c
index efe71d8..2f328bb 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -11258,6 +11258,17 @@
    	.write		= SPI_CHIP_WRITE256, /* Multi I/O supported */
    	.read		= SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
    	.voltage	= {1700, 2000},
+		.reg_bits	=
+		{
+			/*
+			 * There is also a volatile lock register per 64KiB sector, which is not
+			 * mutually exclusive with BP-based protection.
+			 */
+			.srp    = {STATUS1, 7, RW},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+			.tb     = {STATUS1, 5, RW},
+		},
+		.decode_range	= DECODE_RANGE_SPI25,
    },

{
@@ -11292,6 +11303,17 @@
    	.write		= SPI_CHIP_WRITE256, /* Multi I/O supported */
    	.read		= SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
    	.voltage	= {2700, 3600},
+		.reg_bits	=
+		{
+			/*
+			 * There is also a volatile lock register per 64KiB sector, which is not
+			 * mutually exclusive with BP-based protection.
+			 */
+			.srp    = {STATUS1, 7, RW},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+			.tb     = {STATUS1, 5, RW},
+		},
+		.decode_range	= DECODE_RANGE_SPI25,
    },

{
@@ -11326,6 +11348,17 @@
    	.write		= SPI_CHIP_WRITE256, /* Multi I/O supported */
    	.read		= SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
    	.voltage	= {1700, 2000},
+		.reg_bits	=
+		{
+			/*
+			 * There is also a volatile lock register per 64KiB sector, which is not
+			 * mutually exclusive with BP-based protection.
+			 */
+			.srp    = {STATUS1, 7, RW},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}},
+			.tb     = {STATUS1, 5, RW},
+		},
+		.decode_range	= DECODE_RANGE_SPI25,
    },

{
@@ -11360,6 +11393,17 @@
    	.write		= SPI_CHIP_WRITE256, /* Multi I/O supported */
    	.read		= SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
    	.voltage	= {2700, 3600},
+		.reg_bits	=
+		{
+			/*
+			 * There is also a volatile lock register per 64KiB sector, which is not
+			 * mutually exclusive with BP-based protection.
+			 */
+			.srp    = {STATUS1, 7, RW},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}},
+			.tb     = {STATUS1, 5, RW},
+		},
+		.decode_range	= DECODE_RANGE_SPI25,
    },

{
@@ -11999,6 +12043,13 @@
    	.write		= SPI_CHIP_WRITE256, /* Multi I/O supported */
    	.read		= SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
    	.voltage	= {2700, 3600},
+		.reg_bits	=
+		{
+			.srp    = {STATUS1, 7, RW},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}},
+			.tb     = {STATUS1, 5, RW},
+		},
+		.decode_range	= DECODE_RANGE_SPI25,
    },

{