Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim.
Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/83998?usp=email )
Change subject: flashchips: add GD25B256E and GD25R256E ......................................................................
Patch Set 1:
(2 comments)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/83998/comment/3aaef22f_b53c17f6?usp... : PS1, Line 7461: FEATURE_WRSR_EXT2 From the datasheet you linked, I think `FEATURE_WRSR_EXT2` not needed.
`FEATURE_WRSR_EXT2` means that two bytes of status register are read together at the same time. `FEATURE_WRSR2` and `FEATURE_WRSR3` mean that second byte and third byte can be read individually. Which is what I see in the datasheet. Is this correct?
Also, I know that this line was here before, but it might be wrong?
The models that were in this definition previously were GD25Q256D and GD25Q256E, is it possible that you check their datasheets how status register is read? is it one command for two bytes, or each byte can be read independently?
https://review.coreboot.org/c/flashrom/+/83998/comment/cf6034a4_d4f75ddf?usp... : PS1, Line 7493: SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD I think this needs SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD if all the models have BP4