Nico Huber has posted comments on this change. ( https://review.coreboot.org/23338 )
Change subject: digilent_spi: add a driver for the iCEblink40 development board ......................................................................
Patch Set 6: Code-Review+2
(3 comments)
Sorry for the huge delay. Looks good.
I'll give it a day or two in case you still want to change something, then merge it.
https://review.coreboot.org/#/c/23338/4/digilent_spi.c File digilent_spi.c:
https://review.coreboot.org/#/c/23338/4/digilent_spi.c@221 PS4, Line 221:
Added some more checking of the response.
Thx
https://review.coreboot.org/#/c/23338/4/digilent_spi.c@276 PS4, Line 276: ret = spi_start_io(read_follows, writecnt); : if (ret != 0)
Raised to 252, empirically determined as the actual limit of the payload the hardware can handle. […]
The overhead is already reduced by setting it to 252. Now, I agree, changing the loop likely wouldn't bring a significant speed improve- ment (unless you use asychronous bulk transfers and that gets really complex, see dediprog for example).
https://review.coreboot.org/#/c/23338/6/digilent_spi.c File digilent_spi.c:
https://review.coreboot.org/#/c/23338/6/digilent_spi.c@318 PS6, Line 318: .max_data_read = 252, : .max_data_write = 252, Nit: 252 seems to be 256 - 4 (1B opcode, 3B address). I doubt that anyone would use this interface to program chips with 4B addresses, but if you want to prepare for that, I would reduce it to 251.