Shiyu Sun has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/46089 )
Change subject: realtek_mst_i2c_spi.c: Update wp disable function ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/flashrom/+/46089/1/realtek_mst_i2c_spi.c File realtek_mst_i2c_spi.c:
https://review.coreboot.org/c/flashrom/+/46089/1/realtek_mst_i2c_spi.c@162 PS1, Line 162: 0x10
Q: Need to find out where 0x10 is coming from?
Done
https://review.coreboot.org/c/flashrom/+/46089/1/realtek_mst_i2c_spi.c@165 PS1, Line 165: 0xF0
Q: Need to ask what this low byte represents precisely?
I think from the Realtek's update it's required that last byte be 0x01 to enable the setting on pin value. Other value would considered wrong.
https://review.coreboot.org/c/flashrom/+/46089/1/realtek_mst_i2c_spi.c@175 PS1, Line 175: 0xFE
Q: like 0x10 above, should know a bit better where this value came from?
Done