Shiyu Sun has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/46089 )
Change subject: realtek_mst_i2c_spi.c: Update GPIO pin 88 toggle function ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/flashrom/+/46089/1/realtek_mst_i2c_spi.c File realtek_mst_i2c_spi.c:
https://review.coreboot.org/c/flashrom/+/46089/1/realtek_mst_i2c_spi.c@165 PS1, Line 165: 0xF0
Uh, sorry. The original value is 0xF8, this patchset has 0xF0, and the latest patchset has 0xFE. […]
Hi Angel, I think the switch from 0xF8 to 0xF0 is expected here, the vendor specifically we will need the last byte to be 0x01 in order to enable pin configuration. I have also checked all the patchset and looks like we never use 0xFE here, the only place we do an and with 0xFE is when we write pin value(1 or 0) to register 0xFE3F. Those values are all taken from vendor's suggestion.
So basically when write to 0x104F, we do write (val & 0xF0) | 0x01 and when write to 0xFE3F, we will write (val & 0xFE) | toggle.
Does it make sense?