Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/73493 )
Change subject: tree/: Move max_rom_decode into board_cfg ......................................................................
tree/: Move max_rom_decode into board_cfg
TEST=`./flashrom -p internal --flash-name`.
Change-Id: Ifa077d867f29ca7bf9c47529a9cd23273badec94 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M atapromise.c M board_enable.c M chipset_enable.c M cli_classic.c M drkaiser.c M flashrom.c M include/programmer.h M it8212.c M nic3com.c M nicintel.c M nicnatsemi.c M satamv.c M wbsio_spi.c 13 files changed, 57 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/73493/1
diff --git a/atapromise.c b/atapromise.c index 9beebf1..3cd24bb 100644 --- a/atapromise.c +++ b/atapromise.c @@ -169,7 +169,7 @@ data->bar = bar; data->rom_size = rom_size;
- max_rom_decode.parallel = rom_size; + cfg->bcfg->max_rom_decode.parallel = rom_size; return register_par_master(&par_master_atapromise, BUS_PARALLEL, data); }
diff --git a/board_enable.c b/board_enable.c index efb4131..e45ab48 100644 --- a/board_enable.c +++ b/board_enable.c @@ -620,16 +620,16 @@ msg_pdbg("Enabling IT8705F flash ROM interface write.\n"); if (tmp & 0x02) { /* The data sheet contradicts itself about max size. */ - max_rom_decode.parallel = 1024 * 1024; + bcfg->max_rom_decode.parallel = 1024 * 1024; msg_pinfo("IT8705F with very unusual settings.\n" "Please send the output of "flashrom -V -p internal" to flashrom@flashrom.org\n" "with "IT8705: your board name: flashrom -V" as the subject to help us finish\n" "support for your Super I/O. Thanks.\n"); ret = 1; } else if (tmp & 0x08) { - max_rom_decode.parallel = 512 * 1024; + bcfg->max_rom_decode.parallel = 512 * 1024; } else { - max_rom_decode.parallel = 256 * 1024; + bcfg->max_rom_decode.parallel = 256 * 1024; } /* Safety checks. The data sheet is unclear here: Segments 1+3 * overlap, no segment seems to cover top - 1MB to top - 512kB. @@ -673,7 +673,7 @@ ret = 1; } msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n", - max_rom_decode.parallel); + bcfg->max_rom_decode.parallel); if (ret) { msg_pinfo("Not enabling IT8705F flash write.\n"); } else { @@ -2765,7 +2765,7 @@
/* limit the maximum size of the parallel bus */ if (board->max_rom_decode_parallel) - max_rom_decode.parallel = board->max_rom_decode_parallel * 1024; + cfg->max_rom_decode.parallel = board->max_rom_decode_parallel * 1024;
if (board->enable) { msg_pinfo("Enabling full flash access for board "%s %s"... ", diff --git a/chipset_enable.c b/chipset_enable.c index 84206b2..c93480e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -549,8 +549,8 @@ contiguous = 0; } } - max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); - msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh); + cfg->bcfg->max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); + msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", cfg->bcfg->max_rom_decode.fwh);
return 0; } @@ -1239,18 +1239,18 @@ reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG); if (reg8 & CS5530_ISA_MASTER) { /* We have A0-A23 available. */ - max_rom_decode.parallel = 16 * 1024 * 1024; + cfg->bcfg->max_rom_decode.parallel = 16 * 1024 * 1024; } else { reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG); if (reg8 & CS5530_ENABLE_SA2320) { /* We have A0-19, A20-A23 available. */ - max_rom_decode.parallel = 16 * 1024 * 1024; + cfg->bcfg->max_rom_decode.parallel = 16 * 1024 * 1024; } else if (reg8 & CS5530_ENABLE_SA20) { /* We have A0-19, A20 available. */ - max_rom_decode.parallel = 2 * 1024 * 1024; + cfg->bcfg->max_rom_decode.parallel = 2 * 1024 * 1024; } else { /* A20 and above are not active. */ - max_rom_decode.parallel = 1024 * 1024; + cfg->bcfg->max_rom_decode.parallel = 1024 * 1024; } }
@@ -1356,14 +1356,14 @@ static int enable_flash_amd_768_8111(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { /* Enable decoding of 0xFFB00000 to 0xFFFFFFFF (5 MB). */ - max_rom_decode.lpc = 5 * 1024 * 1024; + cfg->bcfg->max_rom_decode.lpc = 5 * 1024 * 1024; return enable_flash_amd_via(cfg, dev, name, 0xC0); }
static int enable_flash_vt82c586(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { /* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (512 kB) */ - max_rom_decode.parallel = 512 * 1024; + cfg->bcfg->max_rom_decode.parallel = 512 * 1024; return enable_flash_amd_via(cfg, dev, name, 0xC0); }
@@ -1371,7 +1371,7 @@ static int enable_flash_vt82c596(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { /* Enable decoding of 0xFFF00000 to 0xFFFFFFFF. (1 MB) */ - max_rom_decode.parallel = 1024 * 1024; + cfg->bcfg->max_rom_decode.parallel = 1024 * 1024; return enable_flash_amd_via(cfg, dev, name, 0xE0); }
diff --git a/cli_classic.c b/cli_classic.c index da68919..96e0b81 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -524,43 +524,43 @@ /* Returns the number of buses commonly supported by the current programmer and flash chip where the latter * can not be completely accessed due to size/address limits of the programmer. */ static unsigned int count_max_decode_exceedings(const struct flashctx *flash, - const struct decode_sizes *max_rom_decode_) + const struct decode_sizes *max_rom_decode) { unsigned int limitexceeded = 0; uint32_t size = flash->chip->total_size * 1024; enum chipbustype buses = flash->mst->buses_supported & flash->chip->bustype;
- if ((buses & BUS_PARALLEL) && (max_rom_decode_->parallel < size)) { + if ((buses & BUS_PARALLEL) && (max_rom_decode->parallel < size)) { limitexceeded++; msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, - max_rom_decode_->parallel / 1024, "Parallel"); + max_rom_decode->parallel / 1024, "Parallel"); } - if ((buses & BUS_LPC) && (max_rom_decode_->lpc < size)) { + if ((buses & BUS_LPC) && (max_rom_decode->lpc < size)) { limitexceeded++; msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, - max_rom_decode_->lpc / 1024, "LPC"); + max_rom_decode->lpc / 1024, "LPC"); } - if ((buses & BUS_FWH) && (max_rom_decode_->fwh < size)) { + if ((buses & BUS_FWH) && (max_rom_decode->fwh < size)) { limitexceeded++; msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, - max_rom_decode_->fwh / 1024, "FWH"); + max_rom_decode->fwh / 1024, "FWH"); } - if ((buses & BUS_SPI) && (max_rom_decode_->spi < size)) { + if ((buses & BUS_SPI) && (max_rom_decode->spi < size)) { limitexceeded++; msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, - max_rom_decode_->spi / 1024, "SPI"); + max_rom_decode->spi / 1024, "SPI"); } return limitexceeded; } @@ -1064,7 +1064,7 @@
print_chip_support_status(fill_flash->chip);
- unsigned int limitexceeded = count_max_decode_exceedings(fill_flash, &max_rom_decode); + unsigned int limitexceeded = count_max_decode_exceedings(fill_flash, &g_max_rom_decode); if (limitexceeded > 0 && !force) { enum chipbustype commonbuses = fill_flash->mst->buses_supported & fill_flash->chip->bustype;
diff --git a/drkaiser.c b/drkaiser.c index ebf5119..36c9a01 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -106,7 +106,7 @@ data->flash_access = pci_read_word(dev, PCI_MAGIC_DRKAISER_ADDR); pci_write_word(dev, PCI_MAGIC_DRKAISER_ADDR, PCI_MAGIC_DRKAISER_VALUE);
- max_rom_decode.parallel = 128 * 1024; + cfg->bcfg->max_rom_decode.parallel = 128 * 1024;
return register_par_master(&par_master_drkaiser, BUS_PARALLEL, data); } diff --git a/flashrom.c b/flashrom.c index f2ee3a9..a9d34f1 100644 --- a/flashrom.c +++ b/flashrom.c @@ -45,7 +45,7 @@ * Programmers supporting multiple buses can have differing size limits on * each bus. Store the limits for each bus in a common struct. */ -struct decode_sizes max_rom_decode; +struct decode_sizes g_max_rom_decode;
/* If nonzero, used as the start address of bottom-aligned flash. */ unsigned long flashbase; @@ -131,7 +131,7 @@ programmer = prog; /* Initialize all programmer specific data. */ /* Default to unlimited decode sizes. */ - max_rom_decode = (const struct decode_sizes) { + g_max_rom_decode = (const struct decode_sizes) { .parallel = 0xffffffff, .lpc = 0xffffffff, .fwh = 0xffffffff, @@ -144,8 +144,8 @@ /* Default to allowing writes. Broken programmers set this to 0. */ programmer_may_write = true;
- struct board_cfg bcfg = {0}; - struct programmer_cfg cfg = { .bcfg = &bcfg }; + struct board_cfg bcfg = { .max_rom_decode = g_max_rom_decode }; + struct programmer_cfg cfg = { .bcfg = &bcfg, };
if (param) { cfg.params = strdup(param); diff --git a/include/programmer.h b/include/programmer.h index 2477c80..0f60767 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -158,6 +158,13 @@
extern const struct penable chipset_enables[];
+struct decode_sizes { + uint32_t parallel; + uint32_t lpc; + uint32_t fwh; + uint32_t spi; +}; + enum board_match_phase { P1, P2, @@ -168,6 +175,7 @@ int is_laptop; bool laptop_ok; enum chipbustype internal_buses_supported; + struct decode_sizes max_rom_decode; };
struct board_match { @@ -283,14 +291,8 @@
/* flashrom.c */ -struct decode_sizes { - uint32_t parallel; - uint32_t lpc; - uint32_t fwh; - uint32_t spi; -}; // FIXME: These need to be local, not global -extern struct decode_sizes max_rom_decode; +extern struct decode_sizes g_max_rom_decode; extern bool programmer_may_write; extern unsigned long flashbase; char *extract_programmer_param_str(const struct programmer_cfg *cfg, const char *param_name); diff --git a/it8212.c b/it8212.c index 3c1161d..6cee140 100644 --- a/it8212.c +++ b/it8212.c @@ -97,7 +97,7 @@ data->decode_access = pci_read_long(dev, PCI_ROM_ADDRESS); pci_write_long(dev, PCI_ROM_ADDRESS, io_base_addr | 0x01);
- max_rom_decode.parallel = IT8212_MEMMAP_SIZE; + cfg->bcfg->max_rom_decode.parallel = IT8212_MEMMAP_SIZE; return register_par_master(&par_master_it8212, BUS_PARALLEL, data); } const struct programmer_entry programmer_it8212 = { diff --git a/nic3com.c b/nic3com.c index a578d48..25ec05c 100644 --- a/nic3com.c +++ b/nic3com.c @@ -142,7 +142,7 @@ data->internal_conf = internal_conf; data->id = id;
- max_rom_decode.parallel = 128 * 1024; + cfg->bcfg->max_rom_decode.parallel = 128 * 1024;
return register_par_master(&par_master_nic3com, BUS_PARALLEL, data);
diff --git a/nicintel.c b/nicintel.c index feb07b6..0e700b6 100644 --- a/nicintel.c +++ b/nicintel.c @@ -118,7 +118,7 @@ data->nicintel_bar = bar; data->nicintel_control_bar = control_bar;
- max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; + cfg->bcfg->max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; return register_par_master(&par_master_nicintel, BUS_PARALLEL, data); }
diff --git a/nicnatsemi.c b/nicnatsemi.c index 65377dc..f0bfd0b 100644 --- a/nicnatsemi.c +++ b/nicnatsemi.c @@ -111,7 +111,7 @@ * max_rom_decode.parallel = 65536; and the mask in the read/write * functions below wants to be 0x0000FFFF. */ - max_rom_decode.parallel = 131072; + cfg->bcfg->max_rom_decode.parallel = 131072; return register_par_master(&par_master_nicnatsemi, BUS_PARALLEL, data); }
diff --git a/satamv.c b/satamv.c index fea4c2b..8a0cebf 100644 --- a/satamv.c +++ b/satamv.c @@ -196,7 +196,7 @@
/* 512 kByte with two 8-bit latches, and * 4 MByte with additional 3-bit latch. */ - max_rom_decode.parallel = 4 * 1024 * 1024; + cfg->bcfg->max_rom_decode.parallel = 4 * 1024 * 1024; return register_par_master(&par_master_satamv, BUS_PARALLEL, data); }
diff --git a/wbsio_spi.c b/wbsio_spi.c index 9f33b18..d779012 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -206,7 +206,7 @@
msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 kB!\n", __func__); - max_rom_decode.spi = 1024 * 1024; + cfg->max_rom_decode.spi = 1024 * 1024;
struct wbsio_spi_data *data = calloc(1, sizeof(*data)); if (!data) {