Attention is currently required from: Jon Murphy, Edward O'Callaghan, Karthik Ramasubramanian, Felix Held.
Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63422 )
Change subject: sb600spi.c: Use SPI100 bit mappings
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/63422/comment/615b55c0_7c04c78a
PS1, Line 11: Stop using the legacy
: spi100 registers and use the correct ones.
I tried the changes in Dalboz (Picasso SoC) and it is working as expected. […]
Ran on Cezanne and everything looks good
```
<+> Get_device_name test: Pass
<+> Coreboot_ELOG_sanity test: Pass
<+> Host_is_ChromeOS test: Pass
<+> Toggle_WP test: Pass
<+> Erase_and_Write test: Pass
<+> Fail_to_verify test: Pass
<+> Lock test: Pass
<+> Lock_top_quad test: Pass
<+> Lock_bottom_quad test: Pass
<+> Lock_bottom_half test: Pass
<+> Lock_top_half test: Pass
```
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