[flashrom-gerrit] Change in flashrom[master]: [RFC] flashchips: add register bit defintions

[Nikolai Artemiev (Code Review)]

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/58477 )

Change subject: [RFC] flashchips: add register bit defintions
......................................................................

[RFC] flashchips: add register bit defintions

This patch adds a representation for the location and properties of
register bits and fills it out for a few example flashchips.

The representation is centered around describing how bits can be
accessed and modified, rather than the layout of registers. This is
generally easier to work with in code that needs to access specific bits
and typically requires specifying the locations of fewer bits overall.

BUG=b:195381327,b:153800563
TEST=ran writeprotect commands that accessed status register bits
BRANCH=none

Change-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284
Signed-off-by: Nikolai Artemiev 
---
M flash.h
M flashchips.c
2 files changed, 65 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/58477/1

diff --git a/flash.h b/flash.h
index ccae05d..8b3899c 100644
--- a/flash.h
+++ b/flash.h
@@ -183,6 +183,25 @@
 };
 #define MAX_REGISTERS 4

+struct reg_bit_info {
+	/* Register containing the bit */
+	enum flash_reg reg;
+
+	/* Bit index within register */
+	uint8_t bit_index;
+
+	/* Writability of the bit. RW does not guarentee the bit will be
+	 * writable, for example if status register protection is enabled. */
+	enum {
+		RO = 0,
+		RW = 1,
+		OTP = 2
+	} writability;
+};
+
+#define MAX_SRP_BITS 2
+#define MAX_BP_BITS 4
+
 struct flashchip {
    const char *vendor;
    const char *name;
@@ -262,6 +281,17 @@
    /* SPI specific options (TODO: Make it a union in case other bustypes get specific options.) */
    uint8_t wrea_override; /**< override opcode for write extended address register */

+	/* TODO: make this a pointer instead of an embedded structure to avoid
+	 * duplication. For now though, it is better to define these values for
+	 * each chip to avoid accidentally reusing an incompatible definition.
+	 */
+	struct reg_bit_map {
+		 struct reg_bit_info srp[MAX_SRP_BITS + 1]; /* Extra element for terminator */
+		 struct reg_bit_info bp[MAX_BP_BITS + 1]; /* Extra element for terminator */
+		 struct reg_bit_info tb;
+		 struct reg_bit_info sec;
+		 struct reg_bit_info cmp;
+	} reg_bits;
 };

typedef int (*chip_restore_fn_cb_t)(struct flashctx *flash, uint8_t status);
diff --git a/flashchips.c b/flashchips.c
index 0d0a8e2..65c2dcc 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -6346,6 +6346,14 @@
    	.write		= spi_chip_write_256,
    	.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
    	.voltage	= {1695, 1950},
+		.reg_bits	=
+		{
+			.srp    = {{STATUS1, 7, RW}, {STATUS2, 0, RW}},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+			.tb     = {STATUS1, 5, RW},
+			.sec    = {STATUS1, 6, RW},
+			.cmp    = {STATUS2, 6, RW},
+		},
    },

{
@@ -6784,6 +6792,14 @@
    	.write		= spi_chip_write_256,
    	.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
    	.voltage	= {2700, 3600},
+		.reg_bits	=
+		{
+			.srp    = {{STATUS1, 7, RW}, {STATUS2, 0, RW}},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+			.tb     = {STATUS1, 5, RW},
+			.sec    = {STATUS1, 6, RW},
+			.cmp    = {STATUS2, 6, RW},
+		},
    },

{
@@ -6897,8 +6913,15 @@
    	.write		= spi_chip_write_256,
    	.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
    	.voltage	= {2700, 3600},
+		.reg_bits	=
+		{
+			.srp    = {{STATUS1, 7, RW}, {STATUS2, 0, RW}},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+			.tb     = {STATUS1, 5, RW},
+			.sec    = {STATUS1, 6, RW},
+			.cmp    = {STATUS2, 6, RW},
+		},
    },
-
    {
    	.vendor		= "GigaDevice",
    	.name		= "GD25Q80(B)",
@@ -8617,6 +8640,11 @@
    	.write		= spi_chip_write_256,
    	.read		= spi_chip_read, /* Fast read (0x0B) supported */
    	.voltage	= {2700, 3600},
+		.reg_bits	=
+		{
+			.srp    = {{STATUS1, 7, RW}},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}},
+		},
    },

{
@@ -18265,6 +18293,12 @@
    			.block_erase = spi_block_erase_c7,
    		}
    	},
+		.reg_bits	=
+		{
+			.srp    = {{STATUS1, 7, RW}},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+			.tb     = {STATUS1, 5, RW},
+		},
    	.printlock	= spi_prettyprint_status_register_plain, /* TODO: improve */
    	.unlock		= spi_disable_blockprotect,
    	.write		= spi_chip_write_256,