Hello build bot (Jenkins), Nico Huber, HAOUAS Elyes,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/40401
to look at the new patch set (#2).
Change subject: chipset_enable.c: Disable SPI on ICH7 if booted from LPC ......................................................................
chipset_enable.c: Disable SPI on ICH7 if booted from LPC
Commit 92d6a86 ("Refactor Intel Chipset Enables") eliminated a check to disable SPI when ICH7 has booted from LPC, as the hardware does not support it. Therefore, when flashrom probes the SPI bus, it times out waiting for the hardware to react, for each and every SPI flash chip. This results in very long delays and countless instances of the error:
Error: SCIP never cleared!
To prevent this, bring back part of the lost check. Probing for LPC and FWH when booted from SPI does not seem to cause any problems on desktop mainboards with ICH7, so don't disable LPC nor FWH if that is the case.
Tested on ECS 945G-M4 (ICH7, boots from LPC), works without errors.
Change-Id: I5e59e66a2dd16b07f2dca410997fce38ab9c8fd1 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M chipset_enable.c 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/01/40401/2