[flashrom-gerrit] Change in flashrom[master]: ft2232_spi: Revise comments about output pin states

[Nico Huber (Code Review)]

Attention is currently required from: Alan Green, Edward O'Callaghan, Angel Pons, Samir Ibradžić.
Hello Alan Green, Edward O'Callaghan, Angel Pons, Samir Ibradžić,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/flashrom/+/55695

to review the following change.

Change subject: ft2232_spi: Revise comments about output pin states
......................................................................

ft2232_spi: Revise comments about output pin states

The meaning of the variables is easy to misunderstand as some
states are merely implicit: All output pins that are not set
in the `cs_bits` mask will be constantly driven low. This may
be sheer coincidence as all programmers that need additional
pins driven use active-low signals to enable buffers.

While other pins stay low, *all* pins set in the `cs_bits`
mask are supposed to be toggled during SPI transactions.

Also drop some irritating dead code and try to explain things
in a comment.

Change-Id: I2b84ede01759c80f69d5ad17e43783d09ecd1107
Signed-off-by: Nico Huber 
---
M ft2232_spi.c
1 file changed, 21 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/55695/1

diff --git a/ft2232_spi.c b/ft2232_spi.c
index dba979b..e546f6c 100644
--- a/ft2232_spi.c
+++ b/ft2232_spi.c
@@ -86,15 +86,27 @@
 #define BITMODE_BITBANG_NORMAL	1
 #define BITMODE_BITBANG_SPI	2

-/* The variables cs_bits and pindir store the values for the "set data bits low byte" MPSSE command that
- * sets the initial state and the direction of the I/O pins. The pin offsets are as follows:
- * SCK is bit 0.
- * DO  is bit 1.
- * DI  is bit 2.
- * CS  is bit 3.
+/*
+ * The variables `cs_bits` and `pindir` store the values for the
+ * "set data bits low byte" MPSSE command that sets the initial
+ * state and the direction of the I/O pins. `cs_bits` pins default
+ * to high and will be toggled during SPI transactions. All other
+ * output pins will be kept low all the time. On exit, all pins
+ * will be reconfigured as inputs.
  *
- * The default values (set below in ft2232_spi_init) are used for most devices:
- *  value: 0x08  CS=high, DI=low, DO=low, SK=low
+ * The pin offsets are as follows:
+ * TCK/SK is bit 0.
+ * TDI/DO is bit 1.
+ * TDO/DI is bit 2.
+ * TMS/CS is bit 3.
+ * GPIOL0 is bit 4.
+ * GPIOL1 is bit 5.
+ * GPIOL2 is bit 6.
+ * GPIOL3 is bit 7.
+ *
+ * The default values (set below in ft2232_spi_init) are used for
+ * most devices:
+ *  value: 0x08  CS=high,   DI=low,   DO=low,    SK=low
  *    dir: 0x0b  CS=output, DI=input, DO=output, SK=output
  */
 struct ft2232_data {
@@ -218,7 +230,7 @@

msg_pspew("Assert CS#\n");
    	buf[i++] = SET_BITS_LOW;
-		buf[i++] = 0 & ~spi_data->cs_bits; /* assertive */
+		buf[i++] = 0; /* assert CS# pins, all other output pins stay low */
    	buf[i++] = spi_data->pindir;

/* WREN, OP(PROGRAM, ERASE), ADDR, DATA */