Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/74163 )
Change subject: board_enable.c: Avoid excessive forward declarations ......................................................................
board_enable.c: Avoid excessive forward declarations
Dispense with unnecessary C89'isms make the code dramaticaly shorter and to the point.
Change-Id: I5d416a023c17568c6275426edc1edb77268ea331 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M board_enable.c 1 file changed, 85 insertions(+), 148 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/63/74163/1
diff --git a/board_enable.c b/board_enable.c index d9af44e..795d0f3 100644 --- a/board_enable.c +++ b/board_enable.c @@ -64,20 +64,16 @@
void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask) { - uint8_t tmp; - OUTB(reg, port); - tmp = INB(port + 1) & ~mask; + uint8_t tmp = INB(port + 1) & ~mask; OUTB(tmp | (data & mask), port + 1); }
/* Winbond W83697 documentation indicates that the index register has to be written for each access. */ static void sio_mask_alzheimer(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask) { - uint8_t tmp; - OUTB(reg, port); - tmp = INB(port + 1) & ~mask; + uint8_t tmp = INB(port + 1) & ~mask; OUTB(reg, port); OUTB(tmp | (data & mask), port + 1); } @@ -116,10 +112,8 @@ */ static int fdc37b787_gpio50_raise(uint16_t port) { - uint8_t id, val; - OUTB(0x55, port); /* enter conf mode */ - id = sio_read(port, 0x20); + uint8_t id = sio_read(port, 0x20); if (id != 0x44) { msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id); OUTB(0xAA, port); /* leave conf mode */ @@ -128,9 +122,8 @@
sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
- val = sio_read(port, 0xC8); /* GP50 */ - if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */ - { + uint8_t val = sio_read(port, 0xC8); /* GP50 */ + if ((val & 0x1B) != 0x10) { /* output, no invert, GPIO */ msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val); OUTB(0xAA, port); return -1; @@ -252,17 +245,13 @@ */ static uint8_t w836xx_deviceid_hwmon(uint16_t sio_port) { - uint16_t hwmport; - uint16_t hwm_vendorid; - uint8_t hwm_deviceid; - sio_write(sio_port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */ if ((sio_read(sio_port, 0x30) & (1 << 0)) != (1 << 0)) { msg_pinfo("W836xx hardware monitor disabled or does not exist.\n"); return 0; } /* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */ - hwmport = sio_read(sio_port, 0x60) << 8; + uint16_t hwmport = sio_read(sio_port, 0x60) << 8; hwmport |= sio_read(sio_port, 0x61); /* HWM address register = HWM base address + 5. */ hwmport += 5; @@ -275,7 +264,7 @@ /* Set HBACS=1. */ sio_mask_alzheimer(hwmport, 0x4e, 0x80, 0x80); /* Read upper byte of vendor ID. */ - hwm_vendorid = sio_read(hwmport, 0x4f) << 8; + uint16_t hwm_vendorid = sio_read(hwmport, 0x4f) << 8; /* Set HBACS=0. */ sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x80); /* Read lower byte of vendor ID. */ @@ -288,24 +277,22 @@ /* Set Bank=0. */ sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x07); /* Read "chip" ID. We call this one the device ID. */ - hwm_deviceid = sio_read(hwmport, 0x58); + uint8_t hwm_deviceid = sio_read(hwmport, 0x58); return hwm_deviceid; }
void probe_superio_winbond(void) { - struct superio s = {0}; uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0}; - uint16_t *i = winbond_ports; - uint8_t model; uint8_t tmp;
+ struct superio s = {0}; s.vendor = SUPERIO_VENDOR_WINBOND; - for (; *i; i++) { + for (uint16_t *i = winbond_ports; *i; i++) { s.port = *i; /* If we're already in Super I/O config more, the W836xx enter sequence won't hurt. */ w836xx_ext_enter(s.port); - model = sio_read(s.port, 0x20); + uint8_t model = sio_read(s.port, 0x20); /* No response, no point leaving the config mode. */ if (model == 0xff) continue; @@ -373,18 +360,14 @@ } w836xx_ext_leave(s.port); } - return; }
static const struct winbond_chip *winbond_superio_chipdef(void) { - int i; - unsigned int j; - - for (i = 0; i < superio_count; i++) { + for (int i = 0; i < superio_count; i++) { if (superios[i].vendor != SUPERIO_VENDOR_WINBOND) continue; - for (j = 0; j < ARRAY_SIZE(winbond_chips); j++) + for (unsigned int j = 0; j < ARRAY_SIZE(winbond_chips); j++) if (winbond_chips[j].device_id == superios[i].model) return &winbond_chips[j]; } @@ -399,12 +382,10 @@ static int winbond_gpio_set(uint16_t base, enum winbond_id chipid, int pin, int raise) { - const struct winbond_chip *chip = NULL; - const struct winbond_port *gpio; int port = pin / 10; int bit = pin % 10;
- chip = winbond_superio_chipdef(); + const struct winbond_chip *chip = winbond_superio_chipdef(); if (!chip) { msg_perr("\nERROR: No supported Winbond Super I/O found\n"); return -1; @@ -420,7 +401,7 @@ return -1; }
- gpio = &chip->port[port - 1]; + const struct winbond_port *gpio = &chip->port[port - 1];
if (gpio->ldn == 0) { msg_perr("\nERROR: GPIO%d is not supported yet on this" @@ -603,14 +584,13 @@ */ int it8705f_write_enable(uint8_t port) { - uint8_t tmp; int ret = 0;
if (!(internal_buses_supported & BUS_PARALLEL)) return 1;
enter_conf_mode_ite(port); - tmp = sio_read(port, 0x24); + uint8_t tmp = sio_read(port, 0x24); /* Check if at least one flash segment is enabled. */ if (tmp & 0xf0) { /* The IT8705F will respond to LPC cycles and translate them. */ @@ -697,12 +677,10 @@ */ static int it8707f_write_enable(uint8_t port) { - uint8_t tmp; - w836xx_ext_enter(port);
/* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */ - tmp = sio_read(port, 0x23); + uint8_t tmp = sio_read(port, 0x23); tmp |= (1 << 3); sio_write(port, 0x23, tmp);
@@ -738,15 +716,13 @@ static const int bankbase[] = {0, 4, 8, 10, 12}; int gpio_bank = gpio / 8; int gpio_pin = gpio % 8; - uint16_t baseport; - uint8_t id, val;
if (gpio_bank > 4) { msg_perr("PC8736x: Invalid GPIO %d\n", gpio); return -1; }
- id = sio_read(0x2E, 0x20); + uint8_t id = sio_read(0x2E, 0x20); if (id != chipid) { msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n", id, chipid); @@ -754,7 +730,7 @@ }
sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */ - baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); + uint16_t baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) { msg_perr("PC87360: invalid GPIO base address %04x\n", baseport); @@ -764,7 +740,7 @@ sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin); sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
- val = INB(baseport + bankbase[gpio_bank]); + uint8_t val = INB(baseport + bankbase[gpio_bank]); if (raise) val |= 1 << gpio_pin; else @@ -779,11 +755,9 @@ */ static int via_vt823x_gpio_set(uint8_t gpio, int raise) { - struct pci_dev *dev; - uint16_t base; - uint8_t val, bit, offset; + uint8_t val;
- dev = pcidev_find_vendorclass(0x1106, 0x0601); + struct pci_dev *dev = pcidev_find_vendorclass(0x1106, 0x0601); switch (dev->device_id) { case 0x3177: /* VT8235 */ case 0x3227: /* VT8237/VT8237R */ @@ -815,10 +789,10 @@ }
/* We need the I/O Base Address for this board's flash enable. */ - base = pci_read_word(dev, 0x88) & 0xff80; + uint16_t base = pci_read_word(dev, 0x88) & 0xff80;
- offset = 0x4C + gpio / 8; - bit = 0x01 << (gpio % 8); + uint8_t offset = 0x4C + gpio / 8; + uint8_t bit = 0x01 << (gpio % 8);
val = INB(base + offset); if (raise) @@ -870,9 +844,7 @@ */ static int board_msi_kt4v(struct board_cfg *cfg) { - int ret; - - ret = via_vt823x_gpio_set(12, 1); + int ret = via_vt823x_gpio_set(12, 1); w836xx_memw_enable(0x2E);
return ret; @@ -890,17 +862,14 @@ /* * Find where the SMBus host is. ASUS sets it to 0xE800; coreboot sets it to 0x0F00. */ - struct pci_dev *dev; - uint16_t smbba; - uint8_t b;
- dev = pcidev_find(0x8086, 0x7113); /* Intel PIIX4, PM/SMBus function. */ + struct pci_dev *dev = pcidev_find(0x8086, 0x7113); /* Intel PIIX4, PM/SMBus function. */ if (!dev) { msg_perr("\nERROR: Intel PIIX4 PM not found.\n"); return -1; }
- smbba = pci_read_word(dev, 0x90) & 0xfff0; + uint16_t smbba = pci_read_word(dev, 0x90) & 0xfff0;
OUTB(0xFF, smbba); /* Clear previous SMBus status. */ OUTB(0x48 << 1, smbba + 4); @@ -909,7 +878,7 @@ OUTB(0x48, smbba + 2);
/* Wait until SMBus transaction is complete. */ - b = 0x1; + uint8_t b = 0x1; while (b & 0x01) { INB(0x80); b = INB(smbba); @@ -1043,16 +1012,13 @@ */ static int board_ecs_geforce6100sm_m(struct board_cfg *cfg) { - struct pci_dev *dev; - uint32_t tmp; - - dev = pcidev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */ + struct pci_dev *dev = pcidev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */ if (!dev) { msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n"); return -1; }
- tmp = pci_read_byte(dev, 0xE0); + uint32_t tmp = pci_read_byte(dev, 0xE0); tmp &= ~(1 << 3); pci_write_byte(dev, 0xE0, tmp);
@@ -1064,17 +1030,13 @@ */ static int nvidia_mcp_gpio_set(int gpio, int raise) { - struct pci_dev *dev; - uint16_t base, devclass; - uint8_t tmp; - if ((gpio < 0) || (gpio >= 0x40)) { msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio); return -1; }
/* Check for the ISA bridge first. */ - dev = pcidev_find_vendorclass(0x10DE, 0x0601); + struct pci_dev *dev = pcidev_find_vendorclass(0x10DE, 0x0601); switch (dev->device_id) { case 0x0030: /* CK804 */ case 0x0050: /* MCP04 */ @@ -1100,7 +1062,7 @@ msg_perr("MCP SMBus controller could not be found\n"); return -1; } - devclass = pci_read_word(dev, PCI_CLASS_DEVICE); + uint16_t devclass = pci_read_word(dev, PCI_CLASS_DEVICE); if (devclass != 0x0C05) { msg_perr("Unexpected device class %04x for SMBus" " controller\n", devclass); @@ -1112,10 +1074,10 @@ return -1; }
- base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ + uint16_t base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ base += 0xC0;
- tmp = INB(base + gpio); + uint8_t tmp = INB(base + gpio); tmp &= ~0x0F; /* null lower nibble */ tmp |= 0x04; /* gpio -> output. */ if (raise) @@ -1265,26 +1227,21 @@ */ static int board_sun_ultra_40_m2(struct board_cfg *cfg) { - int ret; - uint8_t reg; - uint16_t base; - struct pci_dev *dev; - - ret = nvidia_mcp_gpio4_lower(cfg); + int ret = nvidia_mcp_gpio4_lower(cfg); if (ret) return ret;
- dev = pcidev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */ + struct pci_dev *dev = pcidev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */ if (!dev) { msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n"); return -1; }
- base = pci_read_word(dev, 0xb4); /* some IO BAR? */ + uint16_t base = pci_read_word(dev, 0xb4); /* some IO BAR? */ if (!base) return -1;
- reg = INB(base + 0x4b); + uint8_t reg = INB(base + 0x4b); reg |= 0x10; OUTB(reg, base + 0x4b);
@@ -1307,14 +1264,13 @@ #define DBE6x_BOOT_LOC_FLASH 2 #define DBE6x_BOOT_LOC_FWHUB 3
- msr_t msr; unsigned long boot_loc;
/* Geode only has a single core */ if (msr_setup(0)) return -1;
- msr = msr_read(DBE6x_MSR_DIVIL_BALL_OPTS); + msr_t msr = msr_read(DBE6x_MSR_DIVIL_BALL_OPTS);
if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) == (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT)) @@ -1341,16 +1297,13 @@ */ static int amd_sbxxx_gpio9_raise(struct board_cfg *cfg) { - struct pci_dev *dev; - uint32_t reg; - - dev = pcidev_find(0x1002, 0x4372); /* AMD SMBus controller */ + struct pci_dev *dev = pcidev_find(0x1002, 0x4372); /* AMD SMBus controller */ if (!dev) { msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n"); return -1; }
- reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */ + uint32_t reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */ /* enable output (0: enable, 1: tristate): GPIO9 output enable is at bit 5 in 0xA9 */ reg &= ~((uint32_t)1<<(8+5)); @@ -1367,10 +1320,6 @@ */ static int intel_piix4_gpo_set(unsigned int gpo, int raise) { - unsigned int gpo_byte, gpo_bit; - struct pci_dev *dev; - uint32_t tmp, base; - /* GPO{0,8,27,28,30} are always available. */ static const uint32_t nonmuxed_gpos = 0x58000101;
@@ -1408,7 +1357,7 @@ {0} };
- dev = pcidev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */ + struct pci_dev *dev = pcidev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */ if (!dev) { msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n"); return -1; @@ -1434,11 +1383,11 @@ }
/* PM IO base */ - base = pci_read_long(dev, 0x40) & 0x0000FFC0; + uint32_t base = pci_read_long(dev, 0x40) & 0x0000FFC0;
- gpo_byte = gpo >> 3; - gpo_bit = gpo & 7; - tmp = INB(base + 0x34 + gpo_byte); /* GPO register */ + unsigned int gpo_byte = gpo >> 3; + unsigned int gpo_bit = gpo & 7; + uint32_t tmp = INB(base + 0x34 + gpo_byte); /* GPO register */ if (raise) tmp |= 0x01 << gpo_bit; else @@ -1550,13 +1499,11 @@ {0, 0, 0, 0, 0} /* end marker */ };
- struct pci_dev *dev; - uint16_t base; uint32_t tmp; int i, allowed;
/* First, look for a known LPC bridge */ - dev = pcidev_find_vendorclass(0x8086, 0x0601); /* ISA bridge */ + struct pci_dev *dev = pcidev_find_vendorclass(0x8086, 0x0601); /* ISA bridge */ if (!dev) { msg_perr("\nERROR: No known Intel LPC bridge found.\n"); return -1; @@ -1576,7 +1523,7 @@ * strapped to zero. From some mobile ICH9 version on, this becomes * 6:1. The mask below catches all. */ - base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0; + uint16_t base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
/* Check whether the line is allowed. */ if (gpio < 32) @@ -1808,8 +1755,7 @@ */ static int board_hp_vl400(struct board_cfg *cfg) { - int ret; - ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */ + int ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */ if (!ret) ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */ if (!ret) @@ -1902,10 +1848,8 @@ */ static int board_acorp_6a815epd(struct board_cfg *cfg) { - int ret; - /* Lower Blocks Lock -- pin 7 of PLCC32 */ - ret = intel_ich_gpio_set(22, 1); + int ret = intel_ich_gpio_set(22, 1); if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */ ret = intel_ich_gpio_set(23, 1);
@@ -1918,9 +1862,7 @@ */ static int board_kontron_986lcd_m(struct board_cfg *cfg) { - int ret; - - ret = intel_ich_gpio_set(34, 1); /* #TBL */ + int ret = intel_ich_gpio_set(34, 1); /* #TBL */ if (!ret) ret = intel_ich_gpio_set(35, 1); /* #WP */
@@ -1933,11 +1875,8 @@ */ static int via_apollo_gpo_set(int gpio, int raise) { - struct pci_dev *dev; - uint32_t base, tmp; - /* VT82C686 power management */ - dev = pcidev_find(0x1106, 0x3057); + struct pci_dev *dev = pcidev_find(0x1106, 0x3057); if (!dev) { msg_perr("\nERROR: VT82C686 PM device not found.\n"); return -1; @@ -1947,7 +1886,7 @@ raise ? "Rais" : "Dropp", gpio);
/* Select GPO function on multiplexed pins. */ - tmp = pci_read_byte(dev, 0x54); + uint32_t tmp = pci_read_byte(dev, 0x54); switch (gpio) { case 0: tmp &= ~0x03; @@ -1965,7 +1904,7 @@ pci_write_byte(dev, 0x54, tmp);
/* PM IO base */ - base = pci_read_long(dev, 0x48) & 0x0000FF00; + uint32_t base = pci_read_long(dev, 0x48) & 0x0000FF00;
/* Drop GPO0 */ tmp = INL(base + 0x4C); @@ -2007,17 +1946,14 @@ */ static int sis_gpio0_raise_and_w836xx_memw(struct board_cfg *cfg) { - struct pci_dev *dev; - uint16_t base, temp; - - dev = pcidev_find(0x1039, 0x0962); + struct pci_dev *dev = pcidev_find(0x1039, 0x0962); if (!dev) { msg_perr("Expected south bridge not found\n"); return 1; }
- base = pci_read_word(dev, 0x74); - temp = INW(base + 0x68); + uint16_t base = pci_read_word(dev, 0x74); + uint16_t temp = INW(base + 0x68); temp &= ~(1 << 0); /* Make pin output? */ OUTW(temp, base + 0x68);
@@ -2070,22 +2006,18 @@ */ static int board_mitac_6513wu(struct board_cfg *cfg) { - struct pci_dev *dev; - uint16_t rt_port; - uint8_t val; - - dev = pcidev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */ + struct pci_dev *dev = pcidev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */ if (!dev) { msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n"); return -1; }
- rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa); + uint16_t rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa); if (rt_port == 0) return -1;
/* Configure the GPIO pin. */ - val = INB(rt_port + 0x33); /* GP30 config */ + uint8_t val = INB(rt_port + 0x33); /* GP30 config */ val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */ OUTB(val, rt_port + 0x33);
@@ -2103,10 +2035,8 @@ */ static int board_abit_av8(struct board_cfg *cfg) { - uint8_t val; - /* Raise GPO pins GP22 & GP23 */ - val = INB(0x404E); + uint8_t val = INB(0x404E); val |= 0xC0; OUTB(val, 0x404E);
@@ -2120,12 +2050,9 @@ */ static int it8703f_gpio51_raise(struct board_cfg *cfg) { - uint16_t id, base; - uint8_t tmp; - /* Find the IT8703F. */ w836xx_ext_enter(0x2E); - id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); + uint16_t id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); w836xx_ext_leave(0x2E);
if (id != 0x8701) { @@ -2136,7 +2063,7 @@ /* Get the GP567 I/O base. */ w836xx_ext_enter(0x2E); sio_write(0x2E, 0x07, 0x0C); - base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); + uint16_t base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); w836xx_ext_leave(0x2E);
if (!base) { @@ -2146,7 +2073,7 @@ }
/* Raise GP51. */ - tmp = INB(base); + uint8_t tmp = INB(base); tmp |= 0x02; OUTB(tmp, base);
@@ -2160,8 +2087,6 @@ { int allowed, sio; unsigned int port; - uint16_t base, sioport; - uint8_t tmp;
/* IT87 GPIO configuration table */ static const struct it87cfg { @@ -2179,19 +2104,19 @@
/* Find the Super I/O in the probed list */ for (sio = 0; sio < superio_count; sio++) { - int i; if (superios[sio].vendor != SUPERIO_VENDOR_ITE) continue;
/* Is this device in our list? */ - for (i = 0; it87_gpio_table[i].id; i++) + for (int i = 0; it87_gpio_table[i].id; i++) { if (superios[sio].model == it87_gpio_table[i].id) { cfg = &it87_gpio_table[i]; goto found; } + } }
- if (cfg == NULL) { + if (!cfg) { msg_perr("\nERROR: No IT87 Super I/O GPIO configuration " "found.\n"); return -1; @@ -2215,10 +2140,10 @@ }
/* Read the Simple I/O Base Address Register */ - sioport = superios[sio].port; + uint16_t sioport = superios[sio].port; enter_conf_mode_ite(sioport); sio_write(sioport, 0x07, 0x07); - base = (sio_read(sioport, cfg->base_reg) << 8) | + uint16_t base = (sio_read(sioport, cfg->base_reg) << 8) | sio_read(sioport, cfg->base_reg + 1); exit_conf_mode_ite(sioport);
@@ -2233,7 +2158,7 @@ gpio %= 10;
/* set GPIO. */ - tmp = INB(base + port); + uint8_t tmp = INB(base + port); if (raise) tmp |= 1 << gpio; else @@ -2534,8 +2459,7 @@ }
int ret = 0; - unsigned int i; - for (i = 0; i + 1 < ARRAY_SIZE(board_matches); i++) { + for (unsigned int i = 0; i + 1 < ARRAY_SIZE(board_matches); i++) { const struct board_match *b = &board_matches[i]; if (b->vendor_name == NULL || b->board_name == NULL) { msg_gerr("ERROR: Board enable #%d does not define a vendor and board name.\n"