Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/62888 )
Change subject: ichspi: Define `Write Enable Type (WET)` register under HSFC ......................................................................
ichspi: Define `Write Enable Type (WET)` register under HSFC
This patch moves the `WET` macro definition under HSFC offset to make it more readable.
BUG=b:223630977 TEST=Able to perform read/write/erase operation on brya.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f --- M ichspi.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/62888/1
diff --git a/ichspi.c b/ichspi.c index c1c80e5..9146dac 100644 --- a/ichspi.c +++ b/ichspi.c @@ -81,8 +81,6 @@ #define PCH100_HSFC_FCYCLE_OFF (17 - 16) /* 1-4: FLASH Cycle */ #define PCH100_HSFC_FCYCLE (0xf << PCH100_HSFC_FCYCLE_OFF) /* New HSFC Control bit */ -#define HSFC_WET_OFF (21 - 16) /* 5: Write Enable Type */ -#define HSFC_WET (0x1 << HSFC_WET_OFF)
#define PCH100_FADDR_FLA 0x07ffffff
@@ -141,6 +139,8 @@ #define HSFC_FGO (0x1 << HSFC_FGO_OFF) #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) +#define HSFC_WET_OFF 5 /* 5: Write Enable Type */ +#define HSFC_WET (0x1 << HSFC_WET_OFF) /* 3-7: reserved */ #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)