Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62282 )
Change subject: ichspi: Add Jasper Lake support ......................................................................
ichspi: Add Jasper Lake support
Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Jasper Lake is the same as Elkhart Lake.
BUG=b:221175960 TEST=dedede with `flashrom -p internal --flash-size`. ``` $ flashrom -VVV -p internal --ifd -i fd -i bios -r /tmp/filename.rom <snip> Enabling hardware sequencing by default for 100+ series PCH. OK. No board enable found matching coreboot IDs vendor="Google", model="Magolor". The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Chip identified: GD25Q127C/GD25Q128C Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB. There is only one partition containing the whole address space (0x000000 - 0xffffff). There are 4096 erase blocks with 4096 B each. Added layout entry 00000000 - 00ffffff named complete flash Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading Status register Block protection is disabled. Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset 'Jasper Lake'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00381000 - 00ffffff named bios Added layout entry 00001000 - 00380fff named me restore_power_management: Re-enabling power management. Using regions: "bios", "fd". Reading Status register Block protection is disabled. Reading flash... 0x381000-0xffffff:R Reading 13103104 bytes starting at 0x381000. 000000-0x0fff:R Reading 4096 bytes starting at 0x000000. done. restore_power_management: Re-enabling power management. SUCCESS Restoring PCI config space for 00:1f:5 reg 0xdc restore_power_management: Re-enabling power management. ```
Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d Signed-off-by: Edward O'Callaghan quasisec@google.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/62282 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subratabanik@google.com Reviewed-by: Sam McNally sammc@google.com --- M chipset_enable.c M ich_descriptors.c M ichspi.c M programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 5 files changed, 36 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved Subrata Banik: Looks good to me, approved
diff --git a/chipset_enable.c b/chipset_enable.c index 27ab126..a0bffa0 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -610,6 +610,7 @@ case CHIPSET_ELKHART_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: reg_name = "BIOS_SPI_BC"; gcs = pci_read_long(dev, 0xdc); bild = (gcs >> 7) & 1; @@ -717,6 +718,7 @@ break; case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: boot_straps = boot_straps_apl; break; @@ -749,6 +751,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: bbs = (gcs >> 6) & 0x1; break; @@ -1015,6 +1018,11 @@ return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE); }
+static int enable_flash_jsl(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_JASPER_LAKE); +} + static int enable_flash_apl(struct pci_dev *const dev, const char *const name) { return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); @@ -2129,6 +2137,7 @@ {0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, {0x8086, 0x3197, B_S, NT, "Intel", "Gemini Lake", enable_flash_glk}, {0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk}, + {0x8086, 0x4da4, B_S, DEP, "Intel", "Jasper Lake", enable_flash_jsl}, {0x8086, 0x4b24, B_S, DEP, "Intel", "Elkhart Lake", enable_flash_mcc}, {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, diff --git a/ich_descriptors.c b/ich_descriptors.c index 4d85e08..0eabe95 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -49,6 +49,7 @@ case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: case CHIPSET_ELKHART_LAKE: + case CHIPSET_JASPER_LAKE: return 16; case CHIPSET_100_SERIES_SUNRISE_POINT: return 10; @@ -77,6 +78,7 @@ case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: if (cont->NM <= MAX_NUM_MASTERS) return cont->NM; @@ -115,7 +117,8 @@ "8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg", "9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point", "C620 series Lewisburg", "300 series Cannon Point", "400 series Comet Point", - "500 series Tiger Point", "600 series Alder Point", "Meteor Lake", "Apollo Lake", "Gemini Lake", "Elkhart Lake", + "500 series Tiger Point", "600 series Alder Point", "Meteor Lake", + "Apollo Lake", "Gemini Lake", "Jasper Lake", "Elkhart Lake", }; if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names)) cs = 0; @@ -214,6 +217,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: { uint8_t size_enc; if (idx == 0) { @@ -301,6 +305,7 @@ case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: + case CHIPSET_JASPER_LAKE: return freq_str[1][value]; case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: @@ -358,6 +363,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: has_flill1 = true; break; @@ -482,7 +488,7 @@ cs == CHIPSET_400_SERIES_COMET_POINT || cs == CHIPSET_500_SERIES_TIGER_POINT || cs == CHIPSET_600_SERIES_ALDER_POINT || - cs == CHIPSET_METEOR_LAKE) { + cs == CHIPSET_JASPER_LAKE || cs == CHIPSET_METEOR_LAKE) { const char *const master_names[] = { "BIOS", "ME", "GbE", "unknown", "EC", }; @@ -1047,10 +1053,12 @@ if (content->CSSL == 0x14) return CHIPSET_600_SERIES_ALDER_POINT; if (content->CSSL == 0x03) { - if (content->CSSO == 0x70) - return CHIPSET_METEOR_LAKE; - else + if (content->CSSO == 0x58) return CHIPSET_ELKHART_LAKE; + else if (content->CSSO == 0x6c) + return CHIPSET_JASPER_LAKE; + else if (content->CSSO == 0x70) + return CHIPSET_METEOR_LAKE; } msg_pwarn("Unknown flash descriptor, assuming 500 series compatibility.\n"); return CHIPSET_500_SERIES_TIGER_POINT; @@ -1076,6 +1084,7 @@ case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: /* `freq_read` was repurposed, so can't check on it any more. */ break; @@ -1235,6 +1244,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; @@ -1276,6 +1286,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: mmio_le_writel(control, spibar + PCH100_REG_FDOC); return mmio_le_readl(spibar + PCH100_REG_FDOD); diff --git a/ichspi.c b/ichspi.c index a377247..c25303e 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1802,6 +1802,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: *num_pr = 6; /* Includes GPR0 */ *reg_pr0 = PCH100_REG_FPR0; @@ -1840,6 +1841,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: *num_freg = 16; break; @@ -1900,6 +1902,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: tmp = mmio_readl(spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); @@ -1979,6 +1982,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_BAYTRAIL: case CHIPSET_ELKHART_LAKE: break; @@ -2017,6 +2021,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: break; default: @@ -2058,9 +2063,10 @@ if (ich_spi_mode == ich_auto && (ich_gen == CHIPSET_APOLLO_LAKE || ich_gen == CHIPSET_GEMINI_LAKE || + ich_gen == CHIPSET_JASPER_LAKE || ich_gen == CHIPSET_ELKHART_LAKE || ich_gen == CHIPSET_METEOR_LAKE)) { - msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Elkhart/Meteor Lake.\n"); + msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Jasper/Elkhart/Meteor Lake.\n"); ich_spi_mode = ich_hwseq; }
diff --git a/programmer.h b/programmer.h index 86e45f7..5fb0626 100644 --- a/programmer.h +++ b/programmer.h @@ -353,6 +353,7 @@ CHIPSET_METEOR_LAKE, CHIPSET_APOLLO_LAKE, CHIPSET_GEMINI_LAKE, + CHIPSET_JASPER_LAKE, CHIPSET_ELKHART_LAKE, };
diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 13a1897..4951206 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -128,6 +128,7 @@ "\t- "silvermont" for chipsets from Intel's Silvermont architecture (e.g. Bay Trail),\n" "\t- "apollo" for Intel's Apollo Lake SoC.\n" "\t- "gemini" for Intel's Gemini Lake SoC.\n" +"\t- "jasper" for Intel's Jasper Lake SoC.\n" "\t- "meteor" for Intel's Meteor Lake SoC.\n" "\t- "5" or "ibex" for Intel's 5 series chipsets,\n" "\t- "6" or "cougar" for Intel's 6 series chipsets,\n" @@ -242,6 +243,8 @@ cs = CHIPSET_APOLLO_LAKE; else if (strcmp(csn, "gemini") == 0) cs = CHIPSET_GEMINI_LAKE; + else if (strcmp(csn, "jasper") == 0) + cs = CHIPSET_JASPER_LAKE; else if (strcmp(csn, "elkhart") == 0) cs = CHIPSET_ELKHART_LAKE; else if (strcmp(csn, "meteor") == 0)
12 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one.