Attention is currently required from: David Bartley, Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54968 )
Change subject: flashchips: add support for Winbond W25Q01JV ......................................................................
Patch Set 4:
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/54968/comment/e3c4e52b_071bba5d PS1, Line 17757: /* Full chip erase is fastest, typically takes 200s */
Fair enough, I can start a thread on the mailing list exploring options. […]
The problem is that there is no common use-case to tune the list for. Placing smaller blocks first is better for smaller changes, placing bigger blocks first is better for bigger changes. We don't know in advance what to expect.
My idea how to re-arrange things: * Add an optional function to the programmer drivers that can check if a command is expected to succeed (or rather fail, the most obvious example is Intel's internal programmer that can be configured to only allow a specific set of SPI commands). With such a function, the list of block erasers to consider can be filtered at runtime. * Once we know the set of block erasers that is expected to work, we can apply a heuristic that chooses the biggest block that won't unnecessarily erase unchanged data. Or maybe with a threshold, e.g. prefer 64K over 4K if >80% of the 4K blocks would get erased.
Well, maybe there is one low-hanging fruit: For the erase commandline option (-E), we could iterate over the list in reverse order?