Carl-Daniel Hailfinger has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38477 )
Change subject: Fix typos ......................................................................
Fix typos
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net Change-Id: Ia5ed00c488b0719b2bdd6c8f304900511684f445 --- M atavia.c M flashchips.h 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/38477/1
diff --git a/atavia.c b/atavia.c index fdaaa74..b407a30 100644 --- a/atavia.c +++ b/atavia.c @@ -142,7 +142,7 @@ if (rget_io_perms()) return 1;
- dev = pcidev_init(ata_via, PCI_ROM_ADDRESS); /* Acutally no BAR setup needed at all. */ + dev = pcidev_init(ata_via, PCI_ROM_ADDRESS); /* Actually no BAR setup needed at all. */ if (!dev) return 1;
diff --git a/flashchips.h b/flashchips.h index f02958c..14ab6de 100644 --- a/flashchips.h +++ b/flashchips.h @@ -602,7 +602,7 @@ #define PMC_PM49FL004 0x6E
/* - * The Sanyo chip found so far uses SPI, first byte is manufacture code, + * The Sanyo chip found so far uses SPI, first byte is manufacturer code, * second byte is the device code, * third byte is a dummy byte. */