Attention is currently required from: Nico Huber, Edward O'Callaghan, Angel Pons, Sergii Dmytruk. Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58477 )
Change subject: flashchips: add writeprotect bit layout map to chips ......................................................................
Patch Set 21:
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/58477/comment/857dfa9e_3fbd45b4 PS20, Line 6353: .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */ : .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */
Huh, I would've expected BP3 and BP4 to work like the other BPx bits.
Yeah, it's confusing especially since the complement bit is still called CMP. Inconsistency around naming has lead to a bunch of weirdly-wrong code in the cros writeprotect implementation.
I'm not sure how we prevent that inconsistency causing problems as more chips get added, but having a general policy of referring to bits by their actual function (e.g. treating BP3/BP4 as TB/SEC) while noting that they have a different name in the datasheet seems like a decent option.