[flashrom-gerrit] Change in flashrom[master]: internal: Fix board vendor and model memory leaks

[Jacob Garber (Code Review)]

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34846 )

Change subject: internal: Fix board vendor and model memory leaks
......................................................................

internal: Fix board vendor and model memory leaks

The board vendor and model are sometimes specified as arguments during
an internal flash, so make sure they are freed at the end of
initialization.

Change-Id: I9f43708f3b075896be67acec114bc6f390f8c6ca
Signed-off-by: Jacob Garber 
Found-by: Coverity CID 1230664, 1230665
---
M internal.c
1 file changed, 30 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/46/34846/1

diff --git a/internal.c b/internal.c
index 12c0ba3..112702e 100644
--- a/internal.c
+++ b/internal.c
@@ -210,8 +210,10 @@
    }
    free(arg);

-	if (rget_io_perms())
-		return 1;
+	if (rget_io_perms()) {
+		ret = 1;
+		goto cleanup;
+	}

/* Default to Parallel/LPC/FWH flash devices. If a known host controller
     * is found, the host controller init routine sets the
@@ -219,17 +221,22 @@
     */
    internal_buses_supported = BUS_NONSPI;

-	if (try_mtd() == 0)
-		return 0;
+	if (try_mtd() == 0) {
+		ret = 0;
+		goto cleanup;
+	}

/* Initialize PCI access for flash enables */
-	if (pci_init_common() != 0)
-		return 1;
+	if (pci_init_common() != 0) {
+		ret = 1;
+		goto cleanup;
+	}

if (processor_flash_enable()) {
    	msg_perr("Processor detection/init failed.\n"
    		 "Aborting.\n");
-		return 1;
+		ret = 1;
+		goto cleanup;
    }

#if IS_X86
@@ -238,8 +245,10 @@
    		msg_pwarn("Warning: The mainboard IDs set by -p internal:mainboard (%s:%s) do not\n"
    			  "         match the current coreboot IDs of the mainboard (%s:%s).\n",
    			  board_vendor, board_model, cb_vendor, cb_model);
-			if (!force_boardmismatch)
-				return 1;
+			if (!force_boardmismatch) {
+				ret = 1;
+				goto cleanup;
+			}
    		msg_pinfo("Continuing anyway.\n");
    	}
    }
@@ -281,8 +290,9 @@
    if (ret == -2) {
    	msg_perr("WARNING: No chipset found. Flash detection "
    		 "will most likely fail.\n");
-	} else if (ret == ERROR_FATAL)
-		return ret;
+	} else if (ret == ERROR_FATAL) {
+		goto cleanup;
+	}

#if IS_X86
    /* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and
@@ -291,7 +301,8 @@

if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model)) {
    	msg_perr("Aborting to be safe.\n");
-		return 1;
+		ret = 1;
+		goto cleanup;
    }
 #endif

@@ -325,7 +336,13 @@
    		 "========================================================================\n");
    }

-	return 0;
+	ret = 0;
+
+cleanup:
+	free(board_vendor);
+	free(board_model);
+
+	return ret;
 }

static void internal_chip_writeb(const struct flashctx *flash, uint8_t val,