[flashrom-gerrit] Change in flashrom[master]: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq

[Subrata Banik (Code Review)]

Attention is currently required from: Patrick Georgi, Rizwan Qureshi, Stefan Reinauer, Angel Pons, Sridhar Siricilla, Alex Levin, YH Lin, Nico Huber, Martin Roth - Personal, Caveh Jalali, David Hendricks, Tim Wawrzynczak, Nick Vaccaro, Boris Mittelberg.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )

Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................

Patch Set 12:

(3 comments)

Commit Message:

https://review.coreboot.org/c/flashrom/+/61854/comment/cad602cb_90184d3c 
PS7, Line 17: Without this synchronisation being implemented, flashrom is running
            : into below error:
            : 
            : Erasing and writing flash chip... Timeout error between offset
            : 0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED!
            : Uh oh. Erase/write failed. Checking if anything has changed.
> > Please let me know if anything we need to help for moving this CL?
>
> What was said in the first message of the comment thread.

I have reattempted to update the commit msg with setup details and replication steps.

Please suggest if you need better wordings.

https://review.coreboot.org/c/flashrom/+/61854/comment/6d032c44_38e54812 
PS7, Line 25: TEST=Concurrent flashrom access is not throwing timeout.
> > Please let me know if anything we need to help for moving this CL?
>
> What was said in the first message of the comment thread.

I'm able to verify this change on eve device. Updated the same in the commit msg.

File ichspi.c:

https://review.coreboot.org/c/flashrom/+/61854/comment/8fa304e8_c069934d 
PS12, Line 1412: 	}
> Please move out of the read-modify-write. […]

Ack