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Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
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Patch Set 2:
(1 comment)
Patchset:
PS2:
Have you tested that (and with that I mean that the *host* SCIP bit flips when the […]
The SPI controller MMIO registers visible to either masters (CPU and CSE) are separate physical registers
Both the masters are unaware of the of each other's register space
The SPI controller HW is capable to arbitrate between the requests that arrive from individual masters
In regards to H_SCIP. The recommendation is to check this bit before starting a transaction. This indicates a transaction by the same master and not the transactions being served for other masters.
The SBRS register (0xD4) indicates whether a master has an outstanding transaction enqueued or in flight and the transaction type.
hope this clarifies
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