[flashrom-gerrit] [S] Change in flashrom[main]: flashchips: add support for MX77U51250F chip

[Anastasia Klimchuk (Code Review)]

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/82626?usp=email )

Change subject: flashchips: add support for MX77U51250F chip
......................................................................

flashchips: add support for MX77U51250F chip

Add initial support for Macronix MX77U51250F.

BUG=none
BRANCH=none
TEST= Tested read, write and probe on google/fatcat with internal
programmer.

Change-Id: I2c2e94f01dc63f60cf636bc6afe1f033e2a6f83c
Signed-off-by: Bora Guvendik 
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82626
Reviewed-by: Anastasia Klimchuk 
Tested-by: build bot (Jenkins) 
Reviewed-by: DZ 
---
M flashchips.c
M include/flashchips.h
2 files changed, 39 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Anastasia Klimchuk: Looks good to me, approved
  DZ: Looks good to me, but someone else must approve

diff --git a/flashchips.c b/flashchips.c
index d566001..134c3d5 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -12023,6 +12023,44 @@
    	.voltage	= {2700, 3600},
    },

+	{
+		.vendor		= "Macronix",
+		.name		= "MX77U51250F",
+		.bustype	= BUS_SPI,
+		.manufacture_id	= MACRONIX_ID,
+		.model_id	= MACRONIX_MX77U51250F,
+		.total_size	= 65536,
+		.page_size	= 256,
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_CFGR | FEATURE_4BA,
+		.tested		= TEST_OK_PREW,
+		.probe		= PROBE_SPI_RDID,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {4 * 1024, 16384} },
+				.block_erase = SPI_BLOCK_ERASE_20,
+			}, {
+				.eraseblocks = { {32 * 1024, 2048} },
+				.block_erase = SPI_BLOCK_ERASE_52,
+			}, {
+				.eraseblocks = { {64 * 1024, 1024} },
+				.block_erase = SPI_BLOCK_ERASE_D8,
+			}, {
+				.eraseblocks = { {64 * 1024 * 1024, 1} },
+				.block_erase = SPI_BLOCK_ERASE_60,
+			}, {
+				.eraseblocks = { {64 * 1024 * 1024, 1} },
+				.block_erase = SPI_BLOCK_ERASE_C7,
+			}
+		},
+		.printlock	= SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */
+		.unlock		= SPI_DISABLE_BLOCKPROTECT_BP3_SRWD,
+		.write		= SPI_CHIP_WRITE256,
+		.read		= SPI_CHIP_READ, /* Fast read (0x0B) supported */
+		.voltage	= {1650, 2000},
+	},
+
    /* The ST M25P05 is a bit of a problem. It has the same ID as the
     * ST M25P05-A in RES mode, but supports only 128 byte writes instead
     * of 256 byte writes. We rely heavily on the fact that PROBE_SPI_RES1
diff --git a/include/flashchips.h b/include/flashchips.h
index f309a55..f675e4c 100644
--- a/include/flashchips.h
+++ b/include/flashchips.h
@@ -541,6 +541,7 @@
 #define MACRONIX_MX25L6495F	0x9517
 #define MACRONIX_MX25L3255E	0x9e16
 #define MACRONIX_MX77L25650F	0x7519
+#define MACRONIX_MX77U51250F	0x753A
 #define MACRONIX_MX25L3239E     0x2536

#define MACRONIX_MX25R1635F	0x2815