Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/64246 )
Change subject: it85spi.c: Fix some space/tab trivial style issues ......................................................................
it85spi.c: Fix some space/tab trivial style issues
Change-Id: I9192461281f9e760644a241148f4c5100f76da98 Signed-off-by: Edward O'Callaghan quasisec@google.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/64246 Reviewed-by: Anastasia Klimchuk aklm@chromium.org Reviewed-by: Thomas Heijligen src@posteo.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M it85spi.c 1 file changed, 27 insertions(+), 26 deletions(-)
Approvals: build bot (Jenkins): Verified Thomas Heijligen: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved
diff --git a/it85spi.c b/it85spi.c index 51328a8..aa6f90a 100644 --- a/it85spi.c +++ b/it85spi.c @@ -241,53 +241,54 @@ struct it85spi_data *data = flash->mst->spi.data;
it85xx_enter_scratch_rom(data); - /* Exit scratch ROM ONLY when programmer shuts down. Otherwise, the - * temporary flash state may halt the EC. - */ + /* + * Exit scratch ROM ONLY when programmer shuts down. Otherwise, the + * temporary flash state may halt the EC. + */
#ifdef LPC_IO - INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff); - INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/ - INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_low) >> 8) & 0xff); + INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff); + INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/ + INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_low) >> 8) & 0xff); #endif #ifdef LPC_MEMORY - mmio_writeb(0, data->ce_high); + mmio_writeb(0, data->ce_high); #endif - for (i = 0; i < writecnt; ++i) { + for (i = 0; i < writecnt; ++i) { #ifdef LPC_IO - INDIRECT_WRITE(data->shm_io_base, writearr[i]); + INDIRECT_WRITE(data->shm_io_base, writearr[i]); #endif #ifdef LPC_MEMORY - mmio_writeb(writearr[i], data->ce_low); + mmio_writeb(writearr[i], data->ce_low); #endif - } - for (i = 0; i < readcnt; ++i) { + } + for (i = 0; i < readcnt; ++i) { #ifdef LPC_IO - readarr[i] = INDIRECT_READ(data->shm_io_base); + readarr[i] = INDIRECT_READ(data->shm_io_base); #endif #ifdef LPC_MEMORY - readarr[i] = mmio_readb(data->ce_low); + readarr[i] = mmio_readb(data->ce_low); #endif - } + } #ifdef LPC_IO - INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff); - INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/ + INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff); + INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/ #endif #ifdef LPC_MEMORY - mmio_writeb(0, data->ce_high); + mmio_writeb(0, data->ce_high); #endif
- return 0; + return 0; }
static const struct spi_master spi_master_it85xx = { - .max_data_read = 64, - .max_data_write = 64, - .command = it85xx_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, + .max_data_read = 64, + .max_data_write = 64, + .command = it85xx_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, .shutdown = it85xx_shutdown, };