Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/20923 )
Change subject: chipset_enable: Mark Braswell as tested ......................................................................
chipset_enable: Mark Braswell as tested
Reported by Uwe Vieweg: https://mail.coreboot.org/pipermail/flashrom/2017-August/015059.html
Change-Id: Iaf7558af8737af36401f577ca7aba9fd7114a3df Signed-off-by: David Hendricks david.hendricks@gmail.com Reviewed-on: https://review.coreboot.org/20923 Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: Paul Menzel: Looks good to me, but someone else must approve Nico Huber: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/chipset_enable.c b/chipset_enable.c index 6a93d0d..36e2838 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1740,7 +1740,7 @@ {0x8086, 0x1f39, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, {0x8086, 0x1f3a, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, {0x8086, 0x1f3b, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, - {0x8086, 0x229c, NT, "Intel", "Braswell", enable_flash_silvermont}, + {0x8086, 0x229c, OK, "Intel", "Braswell", enable_flash_silvermont}, {0x8086, 0x2310, NT, "Intel", "DH89xxCC (Cave Creek)", enable_flash_pch7}, {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7}, {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0},