Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83144?usp=email )
Change subject: ichspi: Add support for Panther Lake ......................................................................
ichspi: Add support for Panther Lake
This patch adds Panther Lake support into flashrom as per Intel Panther Lake SPI programming doc, number: 815466.
BUG=b:347669091 TEST=Flashrom is able to detect PTL SPI DID and show chipset name as below:
flashrom --flash-name
.... Found chipset "Intel Panther Lake-U/H 12Xe". ....
flashrom -p internal --ifd -i fd -i bios -r /tmp/bios.rom
.... Reading ich_descriptor... done. Assuming chipset 'Panther Lake'. Using regions: "bios", "fd". Reading flash... done. SUCCESS
Change-Id: I99cd8eb7cbb11381f8e8455b06cf90b9db77d8f0 Signed-off-by: Subrata Banik subratabanik@google.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/83144 Reviewed-by: Jamie Ryu jamie.m.ryu@intel.com Reviewed-by: Hsuan-ting Chen roccochen@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Anastasia Klimchuk aklm@chromium.org Reviewed-by: Sam McNally sammc@google.com --- M chipset_enable.c M ich_descriptors.c M ichspi.c M include/programmer.h 4 files changed, 33 insertions(+), 4 deletions(-)
Approvals: Sam McNally: Looks good to me, but someone else must approve Hsuan-ting Chen: Looks good to me, approved build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved Jamie Ryu: Looks good to me, but someone else must approve
diff --git a/chipset_enable.c b/chipset_enable.c index 1c24b92..facf29e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -607,6 +607,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: @@ -715,6 +716,7 @@ case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_C740_SERIES_EMMITSBURG: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: boot_straps = boot_straps_pch500; break; case CHIPSET_APOLLO_LAKE: @@ -750,6 +752,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -1019,6 +1022,11 @@ return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_METEOR_LAKE); }
+static int enable_flash_ptl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_PANTHER_LAKE); +} + static int enable_flash_mcc(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) { return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE); @@ -2186,6 +2194,8 @@ {0x8086, 0x7a8d, B_S, NT, "Intel", "WM690", enable_flash_pch600}, {0x8086, 0x7a8c, B_S, NT, "Intel", "HM670", enable_flash_pch600}, {0x8086, 0x7e23, B_S, DEP, "Intel", "Meteor Lake-P/M", enable_flash_mtl}, + {0x8086, 0xe323, B_S, DEP, "Intel", "Panther Lake-U/H 12Xe", enable_flash_ptl}, + {0x8086, 0xe423, B_S, DEP, "Intel", "Panther Lake-H 4Xe", enable_flash_ptl}, #endif {0}, }; diff --git a/ich_descriptors.c b/ich_descriptors.c index 6de4316..eaf44b0 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -50,6 +50,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_JASPER_LAKE: return 16; @@ -80,6 +81,7 @@ case CHIPSET_APOLLO_LAKE: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: @@ -122,7 +124,7 @@ "C620 series Lewisburg", "C740 series Emmitsburg", "300 series Cannon Point", "400 series Comet Point", "500 series Tiger Point", "600 series Alder Point", "Apollo Lake", "Gemini Lake", "Jasper Lake", "Elkhart Lake", - "Meteor Lake", + "Meteor Lake", "Panther Lake", }; if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names)) cs = 0; @@ -220,6 +222,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -319,6 +322,7 @@ case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_C740_SERIES_EMMITSBURG: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: return freq_str[3][value]; case CHIPSET_ELKHART_LAKE: return freq_str[4][value]; @@ -368,6 +372,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -508,7 +513,9 @@ cs == CHIPSET_500_SERIES_TIGER_POINT || cs == CHIPSET_600_SERIES_ALDER_POINT || cs == CHIPSET_C740_SERIES_EMMITSBURG || - cs == CHIPSET_JASPER_LAKE || cs == CHIPSET_METEOR_LAKE) { + cs == CHIPSET_JASPER_LAKE || + cs == CHIPSET_METEOR_LAKE || + cs == CHIPSET_PANTHER_LAKE) { const char *const master_names[] = { "BIOS", "ME", "GbE", "DevE", "EC", }; @@ -1083,6 +1090,8 @@ return CHIPSET_JASPER_LAKE; else if (content->CSSO == 0x70) return CHIPSET_METEOR_LAKE; + else if (content->CSSO == 0x60) + return CHIPSET_PANTHER_LAKE; } msg_pwarn("Unknown flash descriptor, assuming 500 series compatibility.\n"); return CHIPSET_500_SERIES_TIGER_POINT; @@ -1107,6 +1116,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: @@ -1268,6 +1278,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -1314,6 +1325,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: diff --git a/ichspi.c b/ichspi.c index cc56e0c..f74fb05 100644 --- a/ichspi.c +++ b/ichspi.c @@ -2111,6 +2111,7 @@ case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: *num_pr = 6; /* Includes GPR0 */ *reg_pr0 = PCH100_REG_FPR0; swseq->reg_ssfsc = PCH100_REG_SSFSC; @@ -2151,6 +2152,7 @@ case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: *num_freg = 16; break; default: @@ -2213,6 +2215,7 @@ case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: tmp = mmio_readl(spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08"PRIx32" (DLOCK)\n", tmp); prettyprint_pch100_reg_dlock(tmp); @@ -2294,6 +2297,7 @@ case CHIPSET_BAYTRAIL: case CHIPSET_ELKHART_LAKE: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: break; default: ichspi_bbar = mmio_readl(spibar + ICH9_REG_BBAR); @@ -2333,6 +2337,7 @@ case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: break; default: tmp = mmio_readl(spibar + ICH9_REG_FPB); @@ -2376,8 +2381,9 @@ ich_gen == CHIPSET_GEMINI_LAKE || ich_gen == CHIPSET_JASPER_LAKE || ich_gen == CHIPSET_ELKHART_LAKE || - ich_gen == CHIPSET_METEOR_LAKE)) { - msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Jasper/Elkhart/Meteor Lake.\n"); + ich_gen == CHIPSET_METEOR_LAKE || + ich_gen == CHIPSET_PANTHER_LAKE)) { + msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Jasper/Elkhart/Meteor/Panther Lake.\n"); ich_spi_mode = ich_hwseq; }
diff --git a/include/programmer.h b/include/programmer.h index 8ef6ffd..a90624b 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -363,6 +363,7 @@ CHIPSET_ELKHART_LAKE, /* All chipsets after METEOR_LAKE should support checking BIOS_BM to get read/write access to of FREG0~15 */ CHIPSET_METEOR_LAKE, + CHIPSET_PANTHER_LAKE, };
/* ichspi.c */