Attention is currently required from: Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk.
Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Nikolai Artemiev, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59709
to look at the new patch set (#29).
Change subject: spi25_statusreg.c: support reading/writing security register ......................................................................
spi25_statusreg.c: support reading/writing security register
Not to be confused with "secure registers" of OTP.
Security register is a dedicated status register for security-related bits. You don't write its value directly, issuing special write commands with no data set separate OTP bits to 1 automatically (WRSCUR, WPSEL commands). No WREN is necessary, but at least some datasheets indicate BUSY state after those write commands.
Unlike cases where OTP bit is part of SR and can only be written while in OTP mode, security register can only be written outside of the mode.
The register is found in at least these chips by Macronix: * MX25L6436E * MX25L6445E * MX25L6465E * MX25L6473E
Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae Signed-off-by: Sergii Dmytruk sergii.dmytruk@3mdeb.com --- M include/flash.h M include/spi.h M spi25_statusreg.c 3 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/59709/29