Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/38481 )
Change subject: chipset_enable: Add Kaby Lake U Prem. to known and tested systems ......................................................................
chipset_enable: Add Kaby Lake U Prem. to known and tested systems
Intel Kaby Lake U (with the 9d4e device id) support is available but marked not tested.
Tested reading, writing and erasing both internal flash chips on the Facebook Monolith system with the Intel i3 7100U SoC. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well.
Signed-off-by: Wim Vervoorn wvervoorn@eltan.com Change-Id: Ie35cc896e29baffa63fe9e37c14770001b54e7ec Reviewed-on: https://review.coreboot.org/c/flashrom/+/38481 Tested-by: Nico Huber nico.h@gmx.de Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Angel Pons th3fanbus@gmail.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: Nico Huber: Verified; Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve
diff --git a/chipset_enable.c b/chipset_enable.c index e826d90..3b44d93 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1989,7 +1989,7 @@ {0x8086, 0x9d46, B_S, NT, "Intel", "Skylake Y Premium", enable_flash_pch100}, {0x8086, 0x9d48, B_S, NT, "Intel", "Skylake U Premium", enable_flash_pch100}, {0x8086, 0x9d4b, B_S, NT, "Intel", "Kaby Lake Y w/ iHDCP2.2 Prem.", enable_flash_pch100}, - {0x8086, 0x9d4e, B_S, NT, "Intel", "Kaby Lake U w/ iHDCP2.2 Prem.", enable_flash_pch100}, + {0x8086, 0x9d4e, B_S, DEP, "Intel", "Kaby Lake U w/ iHDCP2.2 Prem.", enable_flash_pch100}, {0x8086, 0x9d50, B_S, NT, "Intel", "Kaby Lake U w/ iHDCP2.2 Base", enable_flash_pch100}, {0x8086, 0x9d51, B_S, NT, "Intel", "Kabe Lake w/ iHDCP2.2 Sample", enable_flash_pch100}, {0x8086, 0x9d53, B_S, NT, "Intel", "Kaby Lake U Base", enable_flash_pch100},