Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83753?usp=email )
Change subject: doc: Convert the doc for MSI JSPI1 ......................................................................
doc: Convert the doc for MSI JSPI1
The doc converted from https://wiki.flashrom.org/MSI_JSPI1
Change-Id: Idd215a3a3a4d62629803a71d360755c43c1ab599 Signed-off-by: Anastasia Klimchuk aklm@flashrom.org Reviewed-on: https://review.coreboot.org/c/flashrom/+/83753 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: David Hendricks david.hendricks@gmail.com --- M doc/user_docs/index.rst A doc/user_docs/msi_jspi1.rst 2 files changed, 53 insertions(+), 0 deletions(-)
Approvals: David Hendricks: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/doc/user_docs/index.rst b/doc/user_docs/index.rst index 6eadfa4..e03789e 100644 --- a/doc/user_docs/index.rst +++ b/doc/user_docs/index.rst @@ -11,4 +11,7 @@ management_engine misc_intel in_system + msi_jspi1 misc_notes + +.. Keep misc notes last diff --git a/doc/user_docs/msi_jspi1.rst b/doc/user_docs/msi_jspi1.rst new file mode 100644 index 0000000..dc20866 --- /dev/null +++ b/doc/user_docs/msi_jspi1.rst @@ -0,0 +1,50 @@ +========= +MSI JSPI1 +========= + +JSPI1 is a 5x2 or 6x2 2.0mm pitch pin header on many MSI motherboards. +It is used to recover from bad boot ROM images. Specifically, +it appears to be used to connect an alternate ROM with a working image. +Pull the #HOLD line low to deselect the onboard SPI ROM, allowing another +SPI ROM to take its place on the bus. Pull the #WP line high to disable write-protection. +Some boards use 1.8V flash chips, while others use 3.3V flash chips; +Check the flash chip datasheet to determine the correct value. + +**JSPI1 (5x2)** + +======== ======== ======== ==== +name pin pin name +======== ======== ======== ==== +VCC 1 2 VCC +MISO 3 4 MOSI +#SS 5 6 SCLK +GND 7 8 GND +#HOLD 9 10 NC +======== ======== ======== ==== + +**JSPI1 (6x2)** + +======== ======== ======== ============ +name pin pin name +======== ======== ======== ============ +VCC 1 2 VCC +SO 3 4 SI +#SS 5 6 CLK +GND 7 8 GND +NC 9 10 NC (no pin) +#WP 11 12 #HOLD +======== ======== ======== ============ + +======== ===================================== +name function +======== ===================================== +VCC Voltage (See flash chip datasheet) +MISO SPI Master In/Slave Out +MOSI SPI Master Out/Slave In +#SS SPI Slave (Chip) Select (active low) +SCLK SPI Clock +GND ground/common +#HOLD SPI hold (active low) +#WP SPI write-protect (active low) +NC Not Connected (or no pin) +======== =====================================