Attention is currently required from: Sam McNally, Edward O'Callaghan, Angel Pons.
Hello Sam McNally, build bot (Jenkins), Edward O'Callaghan, Angel Pons,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/flashrom/+/67867
to review the following change.
Change subject: chipset_enable.c: check return value from rphysmap() call ......................................................................
chipset_enable.c: check return value from rphysmap() call
Port from the ChromiumOS fork of flashrom.
Change-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476 Signed-off-by: Edward O'Callaghan quasisec@google.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/46444 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Sam McNally sammc@google.com Reviewed-by: Angel Pons th3fanbus@gmail.com --- M chipset_enable.c 1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/67/67867/1
diff --git a/chipset_enable.c b/chipset_enable.c index 0dfe267..5195b95 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1002,6 +1002,8 @@ uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00; msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase); void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */ + if (spibar == ERROR_PTR) + return ERROR_FATAL;
/* Enable Flash Writes. * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C).