Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/55353 )
Change subject: flashchips: Add support for Macronix MX66L1G45G ......................................................................
flashchips: Add support for Macronix MX66L1G45G
Tested on Dediprog SF600: Reading and writing works.
Change-Id: I554e828c97d9ec77b08489573a34e176599d2518 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/55353 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M flashchips.c M flashchips.h 2 files changed, 50 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/flashchips.c b/flashchips.c index 950f09b..6310c12 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10074,6 +10074,55 @@ .voltage = {2700, 3600}, },
+ { + .vendor = "Macronix", + .name = "MX66L1G45G", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX66L1G45G, + .total_size = 131072, + .page_size = 256, + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {128 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {128 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + /* TODO: security register and SBLK/SBULK, configuration register */ + .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + /* The ST M25P05 is a bit of a problem. It has the same ID as the * ST M25P05-A in RES mode, but supports only 128 byte writes instead * of 256 byte writes. We rely heavily on the fact that probe_spi_res1 diff --git a/flashchips.h b/flashchips.h index 37eadb2..dd985a7 100644 --- a/flashchips.h +++ b/flashchips.h @@ -511,6 +511,7 @@ #define MACRONIX_MX25L1635D 0x2415 #define MACRONIX_MX25L1635E 0x2515 /* MX25L1635{E} */ #define MACRONIX_MX66L51235F 0x201a /* MX66L51235F, MX25L51245G */ +#define MACRONIX_MX66L1G45G 0x201b /* MX66L1G45G */ #define MACRONIX_MX25U8032E 0x2534 #define MACRONIX_MX25U1635E 0x2535 #define MACRONIX_MX25U3235E 0x2536 /* Same as MX25U6435F */