[flashrom-gerrit] [S] Change in flashrom[main]: flashchips: Add XTX XT25F128B

[Anastasia Klimchuk (Code Review)]

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/82676?usp=email )

Change subject: flashchips: Add XTX XT25F128B
......................................................................

flashchips: Add XTX XT25F128B

XTX XT25F128B is 128M-bit version of XT25F64B.
Tested probe, read, erase and write with FT232H.

Datasheet: https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2304140030_XTX-XT25F128BS...

Change-Id: I37084bd66bc7a8f93d6533ab0d67aa2528786299
Signed-off-by: Robert Marko 
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82676
Tested-by: build bot (Jenkins) 
Reviewed-by: Anastasia Klimchuk 
---
M flashchips.c
M include/flashchips.h
2 files changed, 41 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Anastasia Klimchuk: Looks good to me, approved

diff --git a/flashchips.c b/flashchips.c
index 2065746..34e610a 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -22178,6 +22178,46 @@
    },

{
+		.vendor		= "XTX Technology Limited",
+		.name		= "XT25F128B",
+		.bustype	= BUS_SPI,
+		.manufacture_id	= XTX_ID,
+		.model_id	= XTX_XT25F128B,
+		.total_size	= 16 * 1024,
+		.page_size	= 256,
+		/* Supports SFDP */
+		/* OTP: 4 x 256 bytes */
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
+		.tested		= TEST_OK_PREW,
+		.probe		= PROBE_SPI_RDID,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {4 * 1024, 4096} },
+				.block_erase = SPI_BLOCK_ERASE_20,
+			}, {
+				.eraseblocks = { {32 * 1024, 512} },
+				.block_erase = SPI_BLOCK_ERASE_52,
+			}, {
+				.eraseblocks = { {64 * 1024, 256} },
+				.block_erase = SPI_BLOCK_ERASE_D8,
+			}, {
+				.eraseblocks = { {16 * 1024 * 1024, 1} },
+				.block_erase = SPI_BLOCK_ERASE_60,
+			}, {
+				.eraseblocks = { {16 * 1024 * 1024, 1} },
+				.block_erase = SPI_BLOCK_ERASE_C7,
+			}
+		},
+		.printlock	= SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
+		.unlock		= SPI_DISABLE_BLOCKPROTECT_BP4_SRWD,
+		.write		= SPI_CHIP_WRITE256,
+		.read		= SPI_CHIP_READ,
+		.voltage	= {2700, 3600},
+	},
+
+	{
    	.vendor		= "Zetta Device",
    	.name		= "ZD25D20",
    	.bustype	= BUS_SPI,
diff --git a/include/flashchips.h b/include/flashchips.h
index b8a58b2..d8e8bf1 100644
--- a/include/flashchips.h
+++ b/include/flashchips.h
@@ -1061,6 +1061,7 @@
 #define XTX_ID			0x0B	/* XTX Technology Limited */
 #define XTX_XT25F02E		0x4012
 #define XTX_XT25F64B		0x4017
+#define XTX_XT25F128B		0x4018

#define ZETTA_ID		0xBA	/* Zetta Device */
 #define ZETTA_ZD25D20		0x2012