Jacob Creedon has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/34413 )
Change subject: flashchips: Fill out support for N25Q/MT25Q chips ......................................................................
Patch Set 2:
(2 comments)
See my notes about N25Q vs MT25Q compatibility.
https://review.coreboot.org/c/flashrom/+/34413/2/flashchips.c File flashchips.c:
https://review.coreboot.org/c/flashrom/+/34413/2/flashchips.c@10608 PS2, Line 10608: }, {
Datasheet also mentions 32KiB 0x5c and 0x52.
My understanding here is that the newer MT25 series supports the 32K subsector erase, but the older N25Q does not, however, both use the same JEDEC ID. :-/ There is a application note, TN-25-01 which highlights the differences between N25Q and MT25Q.
https://review.coreboot.org/c/flashrom/+/34413/2/flashchips.c@10616 PS2, Line 10616: .block_erase = spi_block_erase_c7,
Also 0x60 according to the datasheet. The reason that we usually add all […]
This is also a N25Q vs MT25Q issue. Also, I discovered a subtle bug here in that the N25Q512 is a stacked device (two 256Mb dies) whereas the MT25Q512 is monolithic. What this means is that 0xC7 (and 0x60) will work for the MT25Q but not for the N25Q. It would instead would require 0xC4, a special "die erase" command that only applies for stacked devices. Once again, they share the same JEDEC ID :-(
I'm new to this codebase so I don't know the best way to address this issue. Probably the safest thing to do short term is remove the bulk erase command altogether for the 512Mb device. In practice, I've found that erasing a sector at a time is only marginally slower than issuing a bulk erase. Thoughts?
(To be clear here I'm actually working on an MT25Q device)