[flashrom-gerrit] Change in flashrom[master]: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq

[Subrata Banik (Code Review)]

Attention is currently required from: Patrick Georgi, Stefan Reinauer, Angel Pons, Sridhar Siricilla, Alex Levin, YH Lin, Nico Huber, Damien Zammit, Martin Roth, Caveh Jalali, David Hendricks, Tim Wawrzynczak, Nick Vaccaro, Boris Mittelberg.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )

Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................

Patch Set 14:

(1 comment)

Commit Message:

https://review.coreboot.org/c/flashrom/+/61854/comment/84f35221_3f4caee5 
PS7, Line 25: TEST=Concurrent flashrom access is not throwing timeout.
> I just tested this with Lenovo W530 (Ivybridge).  I was able to read the bios region using a layout.
> * 1efdc43 (HEAD) ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
> | * 6289508 (origin/master, master) pcidev: Move scandev_inclass logic from internal to pcidev
> | * bc2e3b6 ft2232_spi.c: Add FTDI FT4233H
> | * 00194ea pcidev: Move pci_get_dev() logic into canonical place
> | * 12dbc4e writeprotect: add {get,set}_wp_mode()
> | * 4cb8464 writeprotect: add set_wp_range()
> | * a548fe5 libflashrom,writeprotect: add flashrom_wp_get_available_ranges()
> | * 2c3a2d6 writeprotect: add get_wp_range() for decoding ranges
> | * 9fc100f flashchips,writeprotect_ranges: add range decoding function
> | * cff87a8 libflashrom,writeprotect: add functions for reading/writing WP configs
> | * 645e5e7 writeprotect.h: add structure to represent chip wp configuration bits
> | * e007908 flash.h,flashchips.c: add writeprotect bit layout map to chips
> |/  
> * b7ea3a9 spi25_statusreg,flashchips: add SR2 read/write support
>
> [damien@zamlap flashrom]$ sudo ./flashrom -pinternal -V --noverify-all --layout ~/w530/layout --image bios -r ~/test.rom  
> flashrom v1.2-629-g1efdc43 on Linux 4.18.0-305.10.2.el8_4.x86_64 (x86_64)
> flashrom is free software, get the source code at https://flashrom.org
>
> Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
> flashrom was built with unknown PCI library, GCC 8.4.1 20200928 (Red Hat 8.4.1-1), little endian
> Command line (9 args): ./flashrom -pinternal -V --noverify-all --layout /home/damien/w530/layout --image bios -r /home/damien/test.rom
> Added layout entry 00000000 - 00000fff named fd
> Added layout entry 00500000 - 00bfffff named bios
> Added layout entry 00003000 - 004fffff named me
> Added layout entry 00001000 - 00002fff named gbe
> Using region: "bios".
> Initializing internal programmer
> /sys/class/mtd/mtd0 does not exist
> Found candidate at: 00000500-00000528
> Found coreboot table at 0x00000500.
> Found candidate at: 00000000-00000c2c
> Found coreboot table at 0x00000000.
> coreboot table found at 0x7ff62000.
> coreboot header(24) checksum: 19b0 table(3092) checksum: 486c entries: 34
> Vendor ID: LENOVO, part ID: ThinkPad W530
> Using Internal DMI decoder.
> DMI string chassis-type: "Laptop"
> Laptop detected via DMI.
> DMI string system-manufacturer: "LENOVO"
> DMI string system-product-name: "24384ZU"
> DMI string system-version: "ThinkPad W530"
> DMI string baseboard-manufacturer: "LENOVO"
> DMI string baseboard-product-name: "24384ZU"
> DMI string baseboard-version: "ThinkPad W530"
> W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect.
> Active config mode, unknown reg 0x20 ID: 00.
> Found chipset "Intel QM77" with PCI ID 8086:1e55.
> Enabling flash write... Root Complex Register Block address = 0xfed1c000
> GCS = 0xc21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI)
> Top Swap: not enabled
> 0x7fffffff/0x7fffffff FWH IDSEL: 0x0
> 0x7fffffff/0x7fffffff FWH IDSEL: 0x0
> 0x7fffffff/0x7fffffff FWH IDSEL: 0x1
> 0x7fffffff/0x7fffffff FWH IDSEL: 0x1
> 0x7fffffff/0x7fffffff FWH IDSEL: 0x2
> 0x7fffffff/0x7fffffff FWH IDSEL: 0x2
> 0x7fffffff/0x7fffffff FWH IDSEL: 0x3
> 0x7fffffff/0x7fffffff FWH IDSEL: 0x3
> 0x7fffffff/0x7fffffff FWH IDSEL: 0x4
> 0x7fffffff/0x7fffffff FWH IDSEL: 0x5
> 0x7fffffff/0x7fffffff FWH IDSEL: 0x6
> 0x7fffffff/0x7fffffff FWH IDSEL: 0x7
> 0x7fffffff/0x7fffffff FWH decode enabled
> 0x7fffffff/0x7fffffff FWH decode enabled
> 0x7fffffff/0x7fffffff FWH decode enabled
> 0x7fffffff/0x7fffffff FWH decode enabled
> 0x7fffffff/0x7fffffff FWH decode enabled
> 0x7fffffff/0x7fffffff FWH decode enabled
> 0x7fffffff/0x7fffffff FWH decode enabled
> 0x7fffffff/0x7fffffff FWH decode enabled
> 0x7fffffff/0x7fffffff FWH decode enabled
> 0x7fffffff/0x7fffffff FWH decode enabled
> 0x7fffffff/0x7fffffff FWH decode enabled
> 0x7fffffff/0x7fffffff FWH decode enabled
> Maximum FWH chip size: 0x100000 bytes
> SPI Read Configuration: prefetching enabled, caching enabled, 
> BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled
> SPIBAR = 0x00007f1ad053d000 + 0x3800
> 0x04: 0xe008 (HSFS)
> HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1
> SPI Configuration is locked down.
> Reading OPCODES... done
> 0x06: 0x3f00 (HSFC)
> HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0
> 0x50: 0x00000a0b (FRAP)
> BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b
> 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only.
> 0x58: 0x0bff0500 FREG1: BIOS region (0x00500000-0x00bfffff) is read-write.
> 0x5C: 0x04ff0003 FREG2: Management Engine region (0x00003000-0x004fffff) is locked.
> 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write.
> Not all flash regions are freely accessible by flashrom. This is most likely
> due to an active ME. Please see https://flashrom.org/ME for details.
> At least some flash regions are read protected. You have to use a flash
> layout and include only accessible regions. For write operations, you'll
> additionally need the --noverify-all switch. See manpage for more details.
> 0x90: 0xc0 (SSFS)
> SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0
> 0x91: 0xf90000 (SSFC)
> SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=1
> 0x94: 0x5006     (PREOP)
> 0x96: 0xb32d     (OPTYPE)
> 0x98: 0x05030201 (OPMENU)
> 0x9c: 0x0bd89f20 (OPMENU+4)
> 0xa0: 0x00000000 (BBAR)
> 0xc4: 0x00802005 (LVSCC)
> LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1
> 0xc8: 0x00002005 (UVSCC)
> UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20
> 0xd0: 0x00000000 (FPB)
> Enabling hardware sequencing due to multiple flash chips detected.
> OK.
> The following protocols are supported: Programmer-specific.
> Probing for Programmer Opaque flash chip, 0 kB: Hardware sequencing reports 2 attached SPI flash chips with a combined density of 12288 kB.
> Added layout entry 00000000 - 00bfffff named complete flash
> Found Programmer flash chip "Opaque flash chip" (12288 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
> Found Programmer flash chip "Opaque flash chip" (12288 kB, Programmer-specific).
> Reading flash... Reading 7340032 bytes starting at 0x500000.
> done.
> Restoring MMIO space at 0x7f1ad05408a0
> $

Thanks Damien for great help.