Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/59016 )
Change subject: hwaccess: replace calls to pci_(r)mmio_XXX with underlaying function ......................................................................
hwaccess: replace calls to pci_(r)mmio_XXX with underlaying function
pci_(r)mmio_XXX functions are only defines of (r)mmio_XXX. Remove this wrapper.
Change-Id: Iee3d3a3ba61586117b79c005a47e1bb661e21437 Signed-off-by: Thomas Heijligen thomas.heijligen@secunet.com --- M atapromise.c M drkaiser.c M gfxnvidia.c M hwaccess.h M it8212.c M nicintel.c M nicintel_eeprom.c M nicintel_spi.c M ogp_spi.c M satamv.c M satasii.c 11 files changed, 67 insertions(+), 76 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/16/59016/1
diff --git a/atapromise.c b/atapromise.c index 0c187e3..ca2e70d 100644 --- a/atapromise.c +++ b/atapromise.c @@ -102,7 +102,7 @@ static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr) { atapromise_limit_chip(flash->chip); - return pci_mmio_readb(atapromise_bar + (addr & ADDR_MASK)); + return mmio_le_readb(atapromise_bar + (addr & ADDR_MASK)); }
static const struct par_master par_master_atapromise = { diff --git a/drkaiser.c b/drkaiser.c index 27c15fb..9382a1c 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -40,13 +40,13 @@ static void drkaiser_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { - pci_mmio_writeb(val, drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); + mmio_le_writeb(val, drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); }
static uint8_t drkaiser_chip_readb(const struct flashctx *flash, const chipaddr addr) { - return pci_mmio_readb(drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); + return mmio_le_readb(drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); }
static const struct par_master par_master_drkaiser = { diff --git a/gfxnvidia.c b/gfxnvidia.c index 048471d..d4aa968 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -61,13 +61,13 @@ static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { - pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); + mmio_le_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); }
static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash, const chipaddr addr) { - return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); + return mmio_le_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); }
static const struct par_master par_master_gfxnvidia = { diff --git a/hwaccess.h b/hwaccess.h index 46335f3..8d7e857 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -50,21 +50,12 @@ uint8_t mmio_le_readb(const void *addr); uint16_t mmio_le_readw(const void *addr); uint32_t mmio_le_readl(const void *addr); -#define pci_mmio_writeb mmio_le_writeb -#define pci_mmio_writew mmio_le_writew -#define pci_mmio_writel mmio_le_writel -#define pci_mmio_readb mmio_le_readb -#define pci_mmio_readw mmio_le_readw -#define pci_mmio_readl mmio_le_readl void rmmio_writeb(uint8_t val, void *addr); void rmmio_writew(uint16_t val, void *addr); void rmmio_writel(uint32_t val, void *addr); void rmmio_le_writeb(uint8_t val, void *addr); void rmmio_le_writew(uint16_t val, void *addr); void rmmio_le_writel(uint32_t val, void *addr); -#define pci_rmmio_writeb rmmio_le_writeb -#define pci_rmmio_writew rmmio_le_writew -#define pci_rmmio_writel rmmio_le_writel void rmmio_valb(void *addr); void rmmio_valw(void *addr); void rmmio_vall(void *addr); diff --git a/it8212.c b/it8212.c index e47f6f8..0013f50 100644 --- a/it8212.c +++ b/it8212.c @@ -34,12 +34,12 @@
static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { - pci_mmio_writeb(val, it8212_bar + (addr & IT8212_MEMMAP_MASK)); + mmio_le_writeb(val, it8212_bar + (addr & IT8212_MEMMAP_MASK)); }
static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr addr) { - return pci_mmio_readb(it8212_bar + (addr & IT8212_MEMMAP_MASK)); + return mmio_le_readb(it8212_bar + (addr & IT8212_MEMMAP_MASK)); }
static const struct par_master par_master_it8212 = { diff --git a/nicintel.c b/nicintel.c index c5b9012..8f4473b 100644 --- a/nicintel.c +++ b/nicintel.c @@ -43,13 +43,13 @@ static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { - pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); + mmio_le_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); }
static uint8_t nicintel_chip_readb(const struct flashctx *flash, const chipaddr addr) { - return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); + return mmio_le_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); }
static const struct par_master par_master_nicintel = { @@ -104,7 +104,7 @@ * what we should do with it. Write 0x0001 because we have nothing * better to do with our time. */ - pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR); + rmmio_le_writew(0x0001, nicintel_control_bar + CSR_FCR);
max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; return register_par_master(&par_master_nicintel, BUS_PARALLEL, NULL); diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index 5887073..eb90265 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -121,7 +121,7 @@ if (nicintel_pci->device_id == UNPROG_DEVICE) flash->chip->total_size = 16; /* Fall back to minimum supported size. */ else { - uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); + uint32_t tmp = mmio_le_readl(nicintel_eebar + EEC); tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK); switch (tmp) { case 7: @@ -149,12 +149,12 @@ static int nicintel_ee_read_word(unsigned int addr, uint16_t *data) { uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR); - pci_mmio_writel(tmp, nicintel_eebar + EERD); + mmio_le_writel(tmp, nicintel_eebar + EERD);
/* Poll done flag. 10.000.000 cycles seem to be enough. */ uint32_t i; for (i = 0; i < MAX_ATTEMPTS; i++) { - tmp = pci_mmio_readl(nicintel_eebar + EERD); + tmp = mmio_le_readl(nicintel_eebar + EERD); if (tmp & BIT(EERD_DONE)) { *data = (tmp >> EERD_DATA) & 0xffff; return 0; @@ -201,12 +201,12 @@ eewr = addr << EEWR_ADDR; eewr |= data << EEWR_DATA; eewr |= BIT(EEWR_CMDV); - pci_mmio_writel(eewr, nicintel_eebar + EEWR); + mmio_le_writel(eewr, nicintel_eebar + EEWR);
programmer_delay(5); int i; for (i = 0; i < MAX_ATTEMPTS; i++) - if (pci_mmio_readl(nicintel_eebar + EEWR) & BIT(EEWR_DONE)) + if (mmio_le_readl(nicintel_eebar + EEWR) & BIT(EEWR_DONE)) return 0; return -1; } @@ -282,12 +282,12 @@ { uint32_t tmp;
- tmp = pci_mmio_readl(nicintel_eebar + reg); + tmp = mmio_le_readl(nicintel_eebar + reg); if (val) tmp |= BIT(bit); else tmp &= ~BIT(bit); - pci_mmio_writel(tmp, nicintel_eebar + reg); + mmio_le_writel(tmp, nicintel_eebar + reg);
return -1; } @@ -302,7 +302,7 @@ nicintel_ee_bitset(EEC, EE_SI, mosi & BIT(i)); nicintel_ee_bitset(EEC, EE_SCK, 1); if (miso != NULL) { - uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); + uint32_t tmp = mmio_le_readl(nicintel_eebar + EEC); if (tmp & BIT(EE_SO)) out |= BIT(i); } @@ -341,7 +341,7 @@ uint32_t tmp; nicintel_ee_bitset(EEC, EE_REQ, 1);
- tmp = pci_mmio_readl(nicintel_eebar + EEC); + tmp = mmio_le_readl(nicintel_eebar + EEC); if (!(tmp & BIT(EE_GNT))) { msg_perr("Enabling eeprom access failed.\n"); return 1; @@ -400,14 +400,14 @@ if (!done_i20_write) return 0;
- uint32_t flup = pci_mmio_readl(nicintel_eebar + EEC); + uint32_t flup = mmio_le_readl(nicintel_eebar + EEC);
flup |= BIT(EE_FLUPD); - pci_mmio_writel(flup, nicintel_eebar + EEC); + mmio_le_writel(flup, nicintel_eebar + EEC);
int i; for (i = 0; i < MAX_ATTEMPTS; i++) - if (pci_mmio_readl(nicintel_eebar + EEC) & BIT(EE_FLUDONE)) + if (mmio_le_readl(nicintel_eebar + EEC) & BIT(EE_FLUDONE)) return 0;
msg_perr("Flash update failed\n"); @@ -479,7 +479,7 @@
nicintel_pci = dev; if (dev->device_id != UNPROG_DEVICE) { - uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); + uint32_t eec = mmio_le_readl(nicintel_eebar + EEC);
/* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition), diff --git a/nicintel_spi.c b/nicintel_spi.c index 5dcdf7d..6de37ba 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -114,12 +114,12 @@ struct nicintel_spi_data *data = spi_data; uint32_t tmp;
- tmp = pci_mmio_readl(data->spibar + FLA); + tmp = mmio_le_readl(data->spibar + FLA); tmp |= BIT(FL_REQ); - pci_mmio_writel(tmp, data->spibar + FLA); + mmio_le_writel(tmp, data->spibar + FLA);
/* Wait until we are allowed to use the SPI bus. */ - while (!(pci_mmio_readl(data->spibar + FLA) & BIT(FL_GNT))) ; + while (!(mmio_le_readl(data->spibar + FLA) & BIT(FL_GNT))) ; }
static void nicintel_release_spibus(void *spi_data) @@ -127,9 +127,9 @@ struct nicintel_spi_data *data = spi_data; uint32_t tmp;
- tmp = pci_mmio_readl(data->spibar + FLA); + tmp = mmio_le_readl(data->spibar + FLA); tmp &= ~BIT(FL_REQ); - pci_mmio_writel(tmp, data->spibar + FLA); + mmio_le_writel(tmp, data->spibar + FLA); }
static void nicintel_bitbang_set_cs(int val, void *spi_data) @@ -137,10 +137,10 @@ struct nicintel_spi_data *data = spi_data; uint32_t tmp;
- tmp = pci_mmio_readl(data->spibar + FLA); + tmp = mmio_le_readl(data->spibar + FLA); tmp &= ~BIT(FL_CS); tmp |= (val << FL_CS); - pci_mmio_writel(tmp, data->spibar + FLA); + mmio_le_writel(tmp, data->spibar + FLA); }
static void nicintel_bitbang_set_sck(int val, void *spi_data) @@ -148,10 +148,10 @@ struct nicintel_spi_data *data = spi_data; uint32_t tmp;
- tmp = pci_mmio_readl(data->spibar + FLA); + tmp = mmio_le_readl(data->spibar + FLA); tmp &= ~BIT(FL_SCK); tmp |= (val << FL_SCK); - pci_mmio_writel(tmp, data->spibar + FLA); + mmio_le_writel(tmp, data->spibar + FLA); }
static void nicintel_bitbang_set_mosi(int val, void *spi_data) @@ -159,10 +159,10 @@ struct nicintel_spi_data *data = spi_data; uint32_t tmp;
- tmp = pci_mmio_readl(data->spibar + FLA); + tmp = mmio_le_readl(data->spibar + FLA); tmp &= ~BIT(FL_SI); tmp |= (val << FL_SI); - pci_mmio_writel(tmp, data->spibar + FLA); + mmio_le_writel(tmp, data->spibar + FLA); }
static void nicintel_bitbang_set_sck_set_mosi(int sck, int mosi, void *spi_data) @@ -170,12 +170,12 @@ struct nicintel_spi_data *data = spi_data; uint32_t tmp;
- tmp = pci_mmio_readl(data->spibar + FLA); + tmp = mmio_le_readl(data->spibar + FLA); tmp &= ~BIT(FL_SCK); tmp &= ~BIT(FL_SI); tmp |= (sck << FL_SCK); tmp |= (mosi << FL_SI); - pci_mmio_writel(tmp, data->spibar + FLA); + mmio_le_writel(tmp, data->spibar + FLA); }
static int nicintel_bitbang_get_miso(void *spi_data) @@ -183,7 +183,7 @@ struct nicintel_spi_data *data = spi_data; uint32_t tmp;
- tmp = pci_mmio_readl(data->spibar + FLA); + tmp = mmio_le_readl(data->spibar + FLA); tmp = (tmp >> FL_SO) & 0x1; return tmp; } @@ -193,10 +193,10 @@ struct nicintel_spi_data *data = spi_data; uint32_t tmp;
- tmp = pci_mmio_readl(data->spibar + FLA); + tmp = mmio_le_readl(data->spibar + FLA); tmp &= ~BIT(FL_SCK); tmp |= (sck << FL_SCK); - pci_mmio_writel(tmp, data->spibar + FLA); + mmio_le_writel(tmp, data->spibar + FLA); return (tmp >> FL_SO) & 0x1; }
@@ -218,10 +218,10 @@ uint32_t tmp;
/* Disable writes manually. See the comment about EECD in nicintel_spi_init() for details. */ - tmp = pci_mmio_readl(data->spibar + EECD); + tmp = mmio_le_readl(data->spibar + EECD); tmp &= ~FLASH_WRITES_ENABLED; tmp |= FLASH_WRITES_DISABLED; - pci_mmio_writel(tmp, data->spibar + EECD); + mmio_le_writel(tmp, data->spibar + EECD);
free(data); return 0; @@ -236,13 +236,13 @@ * but other bits with side effects as well. Those other bits must be * left untouched. */ - tmp = pci_mmio_readl(data->spibar + EECD); + tmp = mmio_le_readl(data->spibar + EECD); tmp &= ~FLASH_WRITES_DISABLED; tmp |= FLASH_WRITES_ENABLED; - pci_mmio_writel(tmp, data->spibar + EECD); + mmio_le_writel(tmp, data->spibar + EECD);
/* test if FWE is really set to allow writes */ - tmp = pci_mmio_readl(data->spibar + EECD); + tmp = mmio_le_readl(data->spibar + EECD); if ( (tmp & FLASH_WRITES_DISABLED) || !(tmp & FLASH_WRITES_ENABLED) ) { msg_perr("Enabling flash write access failed.\n"); return 1; @@ -264,7 +264,7 @@ { uint32_t tmp;
- tmp = pci_mmio_readl(data->spibar + FLA); + tmp = mmio_le_readl(data->spibar + FLA); if (tmp & BIT(FL_LOCKED)) { msg_perr("Flash is in Secure Mode. Abort.\n"); return 1; @@ -272,8 +272,8 @@
if (tmp & BIT(FL_ABORT)) { tmp |= BIT(FL_CLR_ERR); - pci_mmio_writel(tmp, data->spibar + FLA); - tmp = pci_mmio_readl(data->spibar + FLA); + mmio_le_writel(tmp, data->spibar + FLA); + tmp = mmio_le_readl(data->spibar + FLA); if (!(tmp & BIT(FL_ABORT))) { msg_perr("Unable to clear Flash Access Error. Abort\n"); return 1; diff --git a/ogp_spi.c b/ogp_spi.c index 2e5e274..001e6bd 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -54,31 +54,31 @@ static void ogp_request_spibus(void *spi_data) { struct ogp_spi_data *data = spi_data; - pci_mmio_writel(1, data->spibar + data->reg_sel); + mmio_le_writel(1, data->spibar + data->reg_sel); }
static void ogp_release_spibus(void *spi_data) { struct ogp_spi_data *data = spi_data; - pci_mmio_writel(0, data->spibar + data->reg_sel); + mmio_le_writel(0, data->spibar + data->reg_sel); }
static void ogp_bitbang_set_cs(int val, void *spi_data) { struct ogp_spi_data *data = spi_data; - pci_mmio_writel(val, data->spibar + data->reg__ce); + mmio_le_writel(val, data->spibar + data->reg__ce); }
static void ogp_bitbang_set_sck(int val, void *spi_data) { struct ogp_spi_data *data = spi_data; - pci_mmio_writel(val, data->spibar + data->reg_sck); + mmio_le_writel(val, data->spibar + data->reg_sck); }
static void ogp_bitbang_set_mosi(int val, void *spi_data) { struct ogp_spi_data *data = spi_data; - pci_mmio_writel(val, data->spibar + data->reg_siso); + mmio_le_writel(val, data->spibar + data->reg_siso); }
static int ogp_bitbang_get_miso(void *spi_data) @@ -86,7 +86,7 @@ struct ogp_spi_data *data = spi_data; uint32_t tmp;
- tmp = pci_mmio_readl(data->spibar + data->reg_siso); + tmp = mmio_le_readl(data->spibar + data->reg_siso); return tmp & 0x1; }
diff --git a/satamv.c b/satamv.c index cdd2f27..e4aa3b3 100644 --- a/satamv.c +++ b/satamv.c @@ -121,7 +121,7 @@ if (mv_bar == ERROR_PTR) return 1;
- tmp = pci_mmio_readl(mv_bar + FLASH_PARAM); + tmp = mmio_le_readl(mv_bar + FLASH_PARAM); msg_pspew("Flash Parameters:\n"); msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7); msg_pspew("Acc2First=0x%01x\n", (tmp >> 3) & 0xf); @@ -138,22 +138,22 @@ msg_pspew("WrHighExt=0x%01x\n", (tmp >> 27) & 0x1); msg_pspew("Reserved[31:28]=0x%01x\n", (tmp >> 28) & 0xf);
- tmp = pci_mmio_readl(mv_bar + EXPANSION_ROM_BAR_CONTROL); + tmp = mmio_le_readl(mv_bar + EXPANSION_ROM_BAR_CONTROL); msg_pspew("Expansion ROM BAR Control:\n"); msg_pspew("ExpROMSz=0x%01x\n", (tmp >> 19) & 0x7);
/* Enable BAR2 mapping to flash */ - tmp = pci_mmio_readl(mv_bar + PCI_BAR2_CONTROL); + tmp = mmio_le_readl(mv_bar + PCI_BAR2_CONTROL); msg_pspew("PCI BAR2 (Flash/NVRAM) Control:\n"); msg_pspew("Bar2En=0x%01x\n", (tmp >> 0) & 0x1); msg_pspew("BAR2TransAttr=0x%01x\n", (tmp >> 1) & 0x1f); msg_pspew("BAR2Sz=0x%01x\n", (tmp >> 19) & 0x7); tmp &= 0xffffffc0; tmp |= 0x0000001f; - pci_rmmio_writel(tmp, mv_bar + PCI_BAR2_CONTROL); + rmmio_le_writel(tmp, mv_bar + PCI_BAR2_CONTROL);
/* Enable flash: GPIO Port Control Register 0x104f0 */ - tmp = pci_mmio_readl(mv_bar + GPIO_PORT_CONTROL); + tmp = mmio_le_readl(mv_bar + GPIO_PORT_CONTROL); msg_pspew("GPIOPortMode=0x%01x\n", (tmp >> 0) & 0x3); if (((tmp >> 0) & 0x3) != 0x2) msg_pinfo("Warning! Either the straps are incorrect or you " @@ -161,7 +161,7 @@ "values!\n"); tmp &= 0xfffffffc; tmp |= 0x2; - pci_rmmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL); + rmmio_le_writel(tmp, mv_bar + GPIO_PORT_CONTROL);
/* Get I/O BAR location. */ addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2); diff --git a/satasii.c b/satasii.c index 321ef7f..5647cd2 100644 --- a/satasii.c +++ b/satasii.c @@ -41,10 +41,10 @@ { uint32_t ctrl_reg; int i = 0; - while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) { + while ((ctrl_reg = mmio_le_readl(sii_bar)) & (1 << 25)) { if (++i > 10000) { msg_perr("%s: control register stuck at %08x, ignoring.\n", - __func__, pci_mmio_readl(sii_bar)); + __func__, mmio_le_readl(sii_bar)); break; } } @@ -60,9 +60,9 @@ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);
- data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val; - pci_mmio_writel(data_reg, (sii_bar + 4)); - pci_mmio_writel(ctrl_reg, sii_bar); + data_reg = (mmio_le_readl((sii_bar + 4)) & ~0xff) | val; + mmio_le_writel(data_reg, (sii_bar + 4)); + mmio_le_writel(ctrl_reg, sii_bar);
satasii_wait_done(); } @@ -75,11 +75,11 @@ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);
- pci_mmio_writel(ctrl_reg, sii_bar); + mmio_le_writel(ctrl_reg, sii_bar);
satasii_wait_done();
- return (pci_mmio_readl(sii_bar + 4)) & 0xff; + return (mmio_le_readl(sii_bar + 4)) & 0xff; }
static const struct par_master par_master_satasii = { @@ -126,7 +126,7 @@ sii_bar += reg_offset;
/* Check if ROM cycle are OK. */ - if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) + if ((id != 0x0680) && (!(mmio_le_readl(sii_bar) & (1 << 26)))) msg_pwarn("Warning: Flash seems unconnected.\n");
return register_par_master(&par_master_satasii, BUS_PARALLEL, NULL);