[flashrom-gerrit] Change in flashrom[master]: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq

[Subrata Banik (Code Review)]

Attention is currently required from: Patrick Georgi, Rizwan Qureshi, Stefan Reinauer, Sridhar Siricilla, Angel Pons, Alex Levin, YH Lin, Nico Huber, Martin Roth, Caveh Jalali, Tim Wawrzynczak, Nick Vaccaro, Boris Mittelberg.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )

Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
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Patch Set 9:

(1 comment)

Commit Message:

https://review.coreboot.org/c/flashrom/+/61854/comment/84850b09_2ca1aab3 
PS7, Line 25: TEST=Concurrent flashrom access is not throwing timeout.
> > Please also test older platforms, not just the newest (also, platforms
> > that are not supported yet don't matter). If you need help with testing
> > you can always ask on the mailing list and IRC.
>
> Sorry, I don't have those older platform POC information. I will try to set a context with those owners informally. Looking at older platform EDS specification, I don't expect anything would behave differently there as this is same HW seq on Intel platform started with SKL. (you can always ask question about how since then so many years AU worked without this bit being implement on older platform, I don't have that answer either with me)

Rephrasing

how since then so many years AU worked without being bothered about checking this SCIP bit in HW SEQ on older platform, I don't have that answer either with me. But for sure SW SEQ platform do use this SCIP bit checking.