David Hendricks has submitted this change. ( https://review.coreboot.org/c/flashrom/+/42386 )
Change subject: flashchips: Add W25Q256JW_DTR ......................................................................
flashchips: Add W25Q256JW_DTR
W25Q256JW currently has two variants, the W25Q256JW with device ID 0x6019 added in commit be4682d and the W25Q256JW_DTR (aka W25Q256JW-IM) with device ID 0x8019 added by this patch.
Winbond W25Q256-series chips have a few device IDs: 0x4019: W25Q256FV 0x6019: W25Q256JW 0x7019: W25Q256JV 0x8019: W25Q256JW_DTR
Hence we need to be more specific with naming than usual to avoid a false positive with wildcards.
Change-Id: I50a6de2c915f9201c458378fcc49130ead73d8c4 Signed-off-by: David Hendricks david.hendricks@gmail.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/42386 Reviewed-by: Simon Buhrow Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M flashchips.c M flashchips.h 2 files changed, 48 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Simon Buhrow: Looks good to me, but someone else must approve
diff --git a/flashchips.c b/flashchips.c index 09ac9b4..8b5b5cc 100644 --- a/flashchips.c +++ b/flashchips.c @@ -16887,6 +16887,53 @@
{ .vendor = "Winbond", + .name = "W25Q256JW_DTR", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q256_DTR, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, + }, + + { + .vendor = "Winbond", .name = "W25Q32.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, diff --git a/flashchips.h b/flashchips.h index 4ae6c07..5b7937f 100644 --- a/flashchips.h +++ b/flashchips.h @@ -948,6 +948,7 @@ #define WINBOND_NEX_W25Q256JV_M 0x7019 /* W25Q256JV_M (QE=0) */ #define WINBOND_NEX_W25Q64JW 0x8017 #define WINBOND_NEX_W25Q128_DTR 0x8018 /* W25Q128JW_DTR */ +#define WINBOND_NEX_W25Q256_DTR 0x8019 /* W25Q256JW_DTR aka W25Q256256JW-IM */
#define WINBOND_ID 0xDA /* Winbond */ #define WINBOND_W19B160BB 0x49